[llvm] [AMDGPU] Use a consistent DwarfEH register flavour (PR #84513)

[Emma Pilkington via llvm-commits]

epilk wrote:

> Thank you for tracking this down! I'm still not sure I understand how the `IsEH` distinction functions generally; did you happen to get an understanding of why the call-site you reference knows it can request with `IsEH == true`? If not, I still don't think we have to deeply understand this as I don't suspect we will ever want to have a split encoding for `IsEH` vs `other`.

It seems like every other targets (just verified this with a quick grep, not certain) is asking for the EH encoding when generating CFI instructions except us, so I guess it seems reasonable to assume that CFI instructions are using EH encodings. Maybe we should switch to asking for `IsEH == true` registers as well for consistency's sake after this patch merges. But yeah, this is a distinction without a difference for us.

https://github.com/llvm/llvm-project/pull/84513