[llvm] 1ec5b1f - [X86] Add missing immediate qualifier to the (V)PCLMULQDQ instruction names
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 11 06:39:39 PDT 2024
Author: Simon Pilgrim
Date: 2024-03-11T13:39:25Z
New Revision: 1ec5b1f483aa154255d919af9abf5eca2fe8635c
URL: https://github.com/llvm/llvm-project/commit/1ec5b1f483aa154255d919af9abf5eca2fe8635c
DIFF: https://github.com/llvm/llvm-project/commit/1ec5b1f483aa154255d919af9abf5eca2fe8635c.diff
LOG: [X86] Add missing immediate qualifier to the (V)PCLMULQDQ instruction names
Added:
Modified:
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/Target/X86/X86SchedAlderlakeP.td
llvm/lib/Target/X86/X86SchedSapphireRapids.td
llvm/lib/Target/X86/X86ScheduleBdVer2.td
llvm/test/TableGen/x86-fold-tables.inc
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index af0ed071c29aba..b65f49527ae5dd 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2491,12 +2491,12 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
WorkingMI->removeOperand(3);
break;
}
- case X86::PCLMULQDQrr:
- case X86::VPCLMULQDQrr:
- case X86::VPCLMULQDQYrr:
- case X86::VPCLMULQDQZrr:
- case X86::VPCLMULQDQZ128rr:
- case X86::VPCLMULQDQZ256rr: {
+ case X86::PCLMULQDQrri:
+ case X86::VPCLMULQDQrri:
+ case X86::VPCLMULQDQYrri:
+ case X86::VPCLMULQDQZrri:
+ case X86::VPCLMULQDQZ128rri:
+ case X86::VPCLMULQDQZ256rri: {
// SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
// SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
unsigned Imm = MI.getOperand(3).getImm();
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index a572d6f84827f3..4a542b7e5a1bb0 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6917,14 +6917,14 @@ def PCLMULCommuteImm : SDNodeXForm<timm, [{
let Predicates = [NoAVX, HasPCLMUL] in {
let Constraints = "$src1 = $dst" in {
let isCommutable = 1 in
- def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
+ def PCLMULQDQrri : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
(int_x86_pclmulqdq VR128:$src1, VR128:$src2, timm:$src3))]>,
Sched<[WriteCLMul]>;
- def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
+ def PCLMULQDQrmi : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
@@ -6935,7 +6935,7 @@ let Predicates = [NoAVX, HasPCLMUL] in {
def : Pat<(int_x86_pclmulqdq (memop addr:$src2), VR128:$src1,
(i8 timm:$src3)),
- (PCLMULQDQrm VR128:$src1, addr:$src2,
+ (PCLMULQDQrmi VR128:$src1, addr:$src2,
(PCLMULCommuteImm timm:$src3))>;
} // Predicates = [NoAVX, HasPCLMUL]
@@ -6943,10 +6943,10 @@ let Predicates = [NoAVX, HasPCLMUL] in {
foreach HI = ["hq","lq"] in
foreach LO = ["hq","lq"] in {
def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}",
- (PCLMULQDQrr VR128:$dst, VR128:$src,
+ (PCLMULQDQrri VR128:$dst, VR128:$src,
!add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>;
def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}",
- (PCLMULQDQrm VR128:$dst, i128mem:$src,
+ (PCLMULQDQrmi VR128:$dst, i128mem:$src,
!add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>;
}
@@ -6954,25 +6954,25 @@ foreach LO = ["hq","lq"] in {
multiclass vpclmulqdq<RegisterClass RC, X86MemOperand MemOp,
PatFrag LdFrag, Intrinsic IntId> {
let isCommutable = 1 in
- def rr : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst),
- (ins RC:$src1, RC:$src2, u8imm:$src3),
- "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
- [(set RC:$dst,
- (IntId RC:$src1, RC:$src2, timm:$src3))]>,
- Sched<[WriteCLMul]>;
-
- def rm : PCLMULIi8<0x44, MRMSrcMem, (outs RC:$dst),
- (ins RC:$src1, MemOp:$src2, u8imm:$src3),
- "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
- [(set RC:$dst,
- (IntId RC:$src1, (LdFrag addr:$src2), timm:$src3))]>,
- Sched<[WriteCLMul.Folded, WriteCLMul.ReadAfterFold]>;
+ def rri : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst),
+ (ins RC:$src1, RC:$src2, u8imm:$src3),
+ "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ [(set RC:$dst,
+ (IntId RC:$src1, RC:$src2, timm:$src3))]>,
+ Sched<[WriteCLMul]>;
+
+ def rmi : PCLMULIi8<0x44, MRMSrcMem, (outs RC:$dst),
+ (ins RC:$src1, MemOp:$src2, u8imm:$src3),
+ "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ [(set RC:$dst,
+ (IntId RC:$src1, (LdFrag addr:$src2), timm:$src3))]>,
+ Sched<[WriteCLMul.Folded, WriteCLMul.ReadAfterFold]>;
// We can commute a load in the first operand by swapping the sources and
// rotating the immediate.
def : Pat<(IntId (LdFrag addr:$src2), RC:$src1, (i8 timm:$src3)),
- (!cast<Instruction>(NAME#"rm") RC:$src1, addr:$src2,
- (PCLMULCommuteImm timm:$src3))>;
+ (!cast<Instruction>(NAME#"rmi") RC:$src1, addr:$src2,
+ (PCLMULCommuteImm timm:$src3))>;
}
let Predicates = [HasAVX, NoVLX_Or_NoVPCLMULQDQ, HasPCLMUL] in
@@ -6986,10 +6986,10 @@ defm VPCLMULQDQY : vpclmulqdq<VR256, i256mem, load,
multiclass vpclmulqdq_aliases_impl<string InstStr, RegisterClass RC,
X86MemOperand MemOp, string Hi, string Lo> {
def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- (!cast<Instruction>(InstStr # "rr") RC:$dst, RC:$src1, RC:$src2,
+ (!cast<Instruction>(InstStr # "rri") RC:$dst, RC:$src1, RC:$src2,
!add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>;
def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- (!cast<Instruction>(InstStr # "rm") RC:$dst, RC:$src1, MemOp:$src2,
+ (!cast<Instruction>(InstStr # "rmi") RC:$dst, RC:$src1, MemOp:$src2,
!add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>;
}
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 8e3e5542826480..4dc5ea3c861125 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -2295,7 +2295,7 @@ def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
}
def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
+def : InstRW<[ADLPWriteResGroup263, ReadAfterVecXLd], (instrs VPCLMULQDQYrmi)>;
def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
let Latency = 9;
diff --git a/llvm/lib/Target/X86/X86SchedSapphireRapids.td b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
index 78c5994ee96470..3c698d2c9f7a01 100644
--- a/llvm/lib/Target/X86/X86SchedSapphireRapids.td
+++ b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
@@ -2665,8 +2665,8 @@ def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((
"^VPUNPCK(H|L)(BW|WD)Zrmk(z?)$")>;
def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instregex "^VPALIGNRZ128rmik(z?)$",
- "^VPCLMULQDQ(Y|Z)rm$")>;
-def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rm)>;
+ "^VPCLMULQDQ(Y|Z)rmi$")>;
+def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rmi)>;
def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
let ReleaseAtCycles = [3, 1];
diff --git a/llvm/lib/Target/X86/X86ScheduleBdVer2.td b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
index c9749979576f27..296504cfc78513 100644
--- a/llvm/lib/Target/X86/X86ScheduleBdVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
@@ -1275,12 +1275,12 @@ def : InstRW<[WritePHAdd.Folded], (instrs PHADDDrm, PHSUBDrm,
defm : PdWriteResXMMPair<WriteCLMul, [PdFPU0, PdFPMMA], 12, [1, 7], 5, 1>;
-def PdWriteVPCLMULQDQrr : SchedWriteRes<[PdFPU0, PdFPMMA]> {
+def PdWriteVPCLMULQDQrri : SchedWriteRes<[PdFPU0, PdFPMMA]> {
let Latency = 12;
let ReleaseAtCycles = [1, 7];
let NumMicroOps = 6;
}
-def : InstRW<[PdWriteVPCLMULQDQrr], (instrs VPCLMULQDQrr)>;
+def : InstRW<[PdWriteVPCLMULQDQrri], (instrs VPCLMULQDQrri)>;
////////////////////////////////////////////////////////////////////////////////
// SSE4A instructions.
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 185311f3923e3a..e0fccd42e47f73 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -2129,7 +2129,7 @@ static const X86FoldTableEntry Table2[] = {
{X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16},
{X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16},
{X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16},
- {X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16},
+ {X86::PCLMULQDQrri, X86::PCLMULQDQrmi, TB_ALIGN_16},
{X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16},
{X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16},
{X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16},
@@ -3058,11 +3058,11 @@ static const X86FoldTableEntry Table2[] = {
{X86::VPBROADCASTWZ128rrkz, X86::VPBROADCASTWZ128rmkz, TB_NO_REVERSE},
{X86::VPBROADCASTWZ256rrkz, X86::VPBROADCASTWZ256rmkz, TB_NO_REVERSE},
{X86::VPBROADCASTWZrrkz, X86::VPBROADCASTWZrmkz, TB_NO_REVERSE},
- {X86::VPCLMULQDQYrr, X86::VPCLMULQDQYrm, 0},
- {X86::VPCLMULQDQZ128rr, X86::VPCLMULQDQZ128rm, 0},
- {X86::VPCLMULQDQZ256rr, X86::VPCLMULQDQZ256rm, 0},
- {X86::VPCLMULQDQZrr, X86::VPCLMULQDQZrm, 0},
- {X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0},
+ {X86::VPCLMULQDQYrri, X86::VPCLMULQDQYrmi, 0},
+ {X86::VPCLMULQDQZ128rri, X86::VPCLMULQDQZ128rmi, 0},
+ {X86::VPCLMULQDQZ256rri, X86::VPCLMULQDQZ256rmi, 0},
+ {X86::VPCLMULQDQZrri, X86::VPCLMULQDQZrmi, 0},
+ {X86::VPCLMULQDQrri, X86::VPCLMULQDQrmi, 0},
{X86::VPCMOVYrrr, X86::VPCMOVYrmr, 0},
{X86::VPCMOVrrr, X86::VPCMOVrmr, 0},
{X86::VPCMPBZ128rri, X86::VPCMPBZ128rmi, 0},
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