[llvm] 7b90a67 - [X86] Assert that the supportedVectorShift* helpers are only called with generic shift opcodes. NFC.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 11 04:22:00 PDT 2024


Author: Simon Pilgrim
Date: 2024-03-11T11:21:48Z
New Revision: 7b90a67fe717338f7ae4e53f6b97d0f29bacde8e

URL: https://github.com/llvm/llvm-project/commit/7b90a67fe717338f7ae4e53f6b97d0f29bacde8e
DIFF: https://github.com/llvm/llvm-project/commit/7b90a67fe717338f7ae4e53f6b97d0f29bacde8e.diff

LOG: [X86] Assert that the supportedVectorShift* helpers are only called with generic shift opcodes. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index eb249b25374a7d..a74901958ac056 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -28926,6 +28926,9 @@ SDValue X86TargetLowering::LowerWin64_INT128_TO_FP(SDValue Op,
 // supported by the Subtarget
 static bool supportedVectorShiftWithImm(EVT VT, const X86Subtarget &Subtarget,
                                         unsigned Opcode) {
+  assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
+         "Unexpected shift opcode");
+
   if (!VT.isSimple())
     return false;
 
@@ -28959,6 +28962,9 @@ bool supportedVectorShiftWithBaseAmnt(EVT VT, const X86Subtarget &Subtarget,
 // natively supported by the Subtarget
 static bool supportedVectorVarShift(EVT VT, const X86Subtarget &Subtarget,
                                     unsigned Opcode) {
+  assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
+         "Unexpected shift opcode");
+
   if (!VT.isSimple())
     return false;
 


        


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