[llvm] [X86][AVX] Fix handling of out-of-bounds shift amounts in AVX2 vector shift nodes (PR #84426)

[Simon Pilgrim via llvm-commits]

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@@ -47291,6 +47291,16 @@ static SDValue combineShiftRightArithmetic(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = combineShiftToPMULH(N, DAG, Subtarget))
     return V;
 
+  APInt ShiftAmt;
+  SDNode *UMinNode = N1.getNode();
+  if (UMinNode->getOpcode() == ISD::UMIN &&
+      ISD::isConstantSplatVector(UMinNode->getOperand(1).getNode(), ShiftAmt) &&
+      ShiftAmt == VT.getScalarSizeInBits() - 1) {
+    SDValue ShrAmtVal = UMinNode->getOperand(0);
+    SDLoc DL(N);
+    return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N0, ShrAmtVal);
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RKSimon wrote:

No, because ISD::SRA nodes treat out of bounds shift amounts as undefined - we must replace it with a X86ISD::VSRAV node as we want the explicit behaviour explained in the issue - which means we can only perform this fold if X86ISD::VSRAV is legal (vXi32 on AVX2 - vXi64 on AVX512F - vXi16 on AVX512BW) - supportedVectorShiftWithImm should handle that for us.

https://github.com/llvm/llvm-project/pull/84426