[llvm] [RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and isGuaranteedNotToBeUndefOrPoison. (PR #84693)
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llvm-commits at lists.llvm.org
Sun Mar 10 13:50:40 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
Integer RISCVISD::SELECT_CC doesn't create poison. If none of the, operands are poison, the result is not poison.
This allows ISD::FREEZE to be hoisted above RISCVISD::SELECT_CC.
---
Patch is 101.37 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/84693.diff
8 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+32)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+10)
- (modified) llvm/test/CodeGen/RISCV/double-convert.ll (+48-58)
- (modified) llvm/test/CodeGen/RISCV/double-round-conv-sat.ll (+288-348)
- (modified) llvm/test/CodeGen/RISCV/float-convert.ll (+23-25)
- (modified) llvm/test/CodeGen/RISCV/float-round-conv-sat.ll (+84-84)
- (modified) llvm/test/CodeGen/RISCV/half-convert.ll (+26-31)
- (modified) llvm/test/CodeGen/RISCV/half-round-conv-sat.ll (+168-168)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9b748cdcf74511..9d1b64ee17cc12 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17041,6 +17041,38 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
return 1;
}
+bool RISCVTargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(
+ SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
+ bool PoisonOnly, unsigned Depth) const {
+
+ // TODO: Add more target nodes.
+ switch (Op.getOpcode()) {
+ case RISCVISD::SELECT_CC:
+ return all_of(Op->ops(), [&](SDValue V) {
+ return DAG.isGuaranteedNotToBeUndefOrPoison(V, PoisonOnly, Depth + 1);
+ });
+ }
+ return TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(
+ Op, DemandedElts, DAG, PoisonOnly, Depth);
+}
+
+bool RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(
+ SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
+ bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
+
+ // TODO: Add more target nodes.
+ switch (Op.getOpcode()) {
+ case RISCVISD::SELECT_CC:
+ // Integer select_cc cannot create poison.
+ // TODO: What are the FP poison semantics?
+ // TODO: This instruction blocks poison from the unselected operand, can
+ // we do anything with that?
+ return !Op.getValueType().isInteger();
+ }
+ return TargetLowering::canCreateUndefOrPoisonForTargetNode(
+ Op, DemandedElts, DAG, PoisonOnly, ConsiderFlags, Depth);
+}
+
const Constant *
RISCVTargetLowering::getTargetConstantFromLoad(LoadSDNode *Ld) const {
assert(Ld && "Unexpected null LoadSDNode");
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index f90cb4df604761..72167be7ae8213 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -585,6 +585,16 @@ class RISCVTargetLowering : public TargetLowering {
const SelectionDAG &DAG,
unsigned Depth) const override;
+ bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(
+ SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
+ bool PoisonOnly, unsigned Depth) const override;
+
+ bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
+ const APInt &DemandedElts,
+ const SelectionDAG &DAG,
+ bool PoisonOnly, bool ConsiderFlags,
+ unsigned Depth) const override;
+
const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
// This method returns the name of a target specific DAG node.
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 3700a18bafc612..96c3aa05a2d682 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -749,47 +749,41 @@ define i64 @fcvt_l_d(double %a) nounwind {
define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_l_d_sat:
; RV32IFD: # %bb.0: # %start
-; RV32IFD-NEXT: addi sp, sp, -32
-; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI12_1)
-; RV32IFD-NEXT: fld fa4, %lo(.LCPI12_1)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: flt.d s0, fa5, fa0
-; RV32IFD-NEXT: neg s1, s0
-; RV32IFD-NEXT: fle.d s2, fa4, fa0
-; RV32IFD-NEXT: neg s3, s2
+; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi
-; RV32IFD-NEXT: and a0, s3, a0
-; RV32IFD-NEXT: or a0, s1, a0
-; RV32IFD-NEXT: feq.d a2, fs0, fs0
-; RV32IFD-NEXT: neg a2, a2
-; RV32IFD-NEXT: lui a4, 524288
-; RV32IFD-NEXT: li a5, 1
; RV32IFD-NEXT: lui a3, 524288
-; RV32IFD-NEXT: bne s2, a5, .LBB12_2
+; RV32IFD-NEXT: li a4, 1
+; RV32IFD-NEXT: lui a2, 524288
+; RV32IFD-NEXT: bne s0, a4, .LBB12_2
; RV32IFD-NEXT: # %bb.1: # %start
-; RV32IFD-NEXT: mv a3, a1
+; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB12_2: # %start
-; RV32IFD-NEXT: and a0, a2, a0
-; RV32IFD-NEXT: beqz s0, .LBB12_4
+; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1)
+; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1)
+; RV32IFD-NEXT: flt.d a4, fa5, fs0
+; RV32IFD-NEXT: beqz a4, .LBB12_4
; RV32IFD-NEXT: # %bb.3:
-; RV32IFD-NEXT: addi a3, a4, -1
+; RV32IFD-NEXT: addi a2, a3, -1
; RV32IFD-NEXT: .LBB12_4: # %start
-; RV32IFD-NEXT: and a1, a2, a3
-; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: feq.d a1, fs0, fs0
+; RV32IFD-NEXT: neg a3, a1
+; RV32IFD-NEXT: and a1, a3, a2
+; RV32IFD-NEXT: neg a2, a4
+; RV32IFD-NEXT: neg a4, s0
+; RV32IFD-NEXT: and a0, a4, a0
+; RV32IFD-NEXT: or a0, a2, a0
+; RV32IFD-NEXT: and a0, a3, a0
+; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
-; RV32IFD-NEXT: addi sp, sp, 32
+; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_l_d_sat:
@@ -807,45 +801,41 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
+; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
+; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
+; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
+; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
-; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s3, s2
-; RV32IZFINXZDINX-NEXT: call __fixdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_1)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_1+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_1)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s3, a0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a3
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
+; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: li a6, 1
-; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: bne s2, a6, .LBB12_2
+; RV32IZFINXZDINX-NEXT: li a4, 1
+; RV32IZFINXZDINX-NEXT: lui a3, 524288
+; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB12_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
-; RV32IZFINXZDINX-NEXT: mv a4, a1
+; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB12_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI12_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI12_1)(a1)
+; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI12_1+4)(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a4, .LBB12_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a4, a5, -1
+; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB12_4: # %start
-; RV32IZFINXZDINX-NEXT: and a1, a2, a4
+; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: and a1, a5, a3
+; RV32IZFINXZDINX-NEXT: neg a2, a2
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: neg a2, a4
+; RV32IZFINXZDINX-NEXT: or a0, a2, a0
+; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
; RV32IZFINXZDINX-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
index 7cdf18e2fea9c0..e128c5d2033493 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
@@ -50,48 +50,42 @@ define signext i32 @test_floor_si32(double %x) {
define i64 @test_floor_si64(double %x) nounwind {
; RV32IFD-LABEL: test_floor_si64:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: addi sp, sp, -32
-; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call floor
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: flt.d s0, fa5, fa0
-; RV32IFD-NEXT: neg s1, s0
-; RV32IFD-NEXT: fle.d s2, fa4, fa0
-; RV32IFD-NEXT: neg s3, s2
+; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi
-; RV32IFD-NEXT: and a0, s3, a0
-; RV32IFD-NEXT: or a0, s1, a0
-; RV32IFD-NEXT: feq.d a2, fs0, fs0
-; RV32IFD-NEXT: neg a2, a2
-; RV32IFD-NEXT: lui a4, 524288
-; RV32IFD-NEXT: li a5, 1
; RV32IFD-NEXT: lui a3, 524288
-; RV32IFD-NEXT: bne s2, a5, .LBB1_2
+; RV32IFD-NEXT: li a4, 1
+; RV32IFD-NEXT: lui a2, 524288
+; RV32IFD-NEXT: bne s0, a4, .LBB1_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: mv a3, a1
+; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB1_2:
-; RV32IFD-NEXT: and a0, a2, a0
-; RV32IFD-NEXT: beqz s0, .LBB1_4
+; RV32IFD-NEXT: lui a1, %hi(.LCPI1_1)
+; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_1)(a1)
+; RV32IFD-NEXT: flt.d a4, fa5, fs0
+; RV32IFD-NEXT: beqz a4, .LBB1_4
; RV32IFD-NEXT: # %bb.3:
-; RV32IFD-NEXT: addi a3, a4, -1
+; RV32IFD-NEXT: addi a2, a3, -1
; RV32IFD-NEXT: .LBB1_4:
-; RV32IFD-NEXT: and a1, a2, a3
-; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: feq.d a1, fs0, fs0
+; RV32IFD-NEXT: neg a3, a1
+; RV32IFD-NEXT: and a1, a3, a2
+; RV32IFD-NEXT: neg a2, a4
+; RV32IFD-NEXT: neg a4, s0
+; RV32IFD-NEXT: and a0, a4, a0
+; RV32IFD-NEXT: or a0, a2, a0
+; RV32IFD-NEXT: and a0, a3, a0
+; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
-; RV32IFD-NEXT: addi sp, sp, 32
+; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_floor_si64:
@@ -109,46 +103,42 @@ define i64 @test_floor_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call floor
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
+; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
+; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
+; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
+; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
-; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s3, s2
-; RV32IZFINXZDINX-NEXT: call __fixdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_1+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s3, a0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a3
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
+; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: li a6, 1
-; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: bne s2, a6, .LBB1_2
+; RV32IZFINXZDINX-NEXT: li a4, 1
+; RV32IZFINXZDINX-NEXT: lui a3, 524288
+; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB1_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a4, a1
+; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB1_2:
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB1_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI1_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI1_1)(a1)
+; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI1_1+4)(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a4, .LBB1_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a4, a5, -1
+; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB1_4:
-; RV32IZFINXZDINX-NEXT: and a1, a2, a4
+; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: and a1, a5, a3
+; RV32IZFINXZDINX-NEXT: neg a2, a2
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: neg a2, a4
+; RV32IZFINXZDINX-NEXT: or a0, a2, a0
+; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
; RV32IZFINXZDINX-NEXT: ret
;
@@ -330,48 +320,42 @@ define signext i32 @test_ceil_si32(double %x) {
define i64 @test_ceil_si64(double %x) nounwind {
; RV32IFD-LABEL: test_ceil_si64:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: addi sp, sp, -32
-; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call ceil
; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_0)(a0)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI5_1)
-; RV32IFD-NEXT: fld fa4, %lo(.LCPI5_1)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: flt.d s0, fa5, fa0
-; RV32IFD-NEXT: neg s1, s0
-; RV32IFD-NEXT: fle.d s2, fa4, fa0
-; RV32IFD-NEXT: neg s3, s2
+; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi
-; RV32IFD-NEXT: and a0, s3, a0
-; RV32IFD-NEXT: or a0, s1, a0
-; RV32IFD-NEXT: feq.d a2, fs0, fs0
-; RV32IFD-NEXT: neg a2, a2
-; RV32IFD-NEXT: lui a4, 524288
-; RV32IFD-NEXT: li a5, 1
; RV32IFD-NEXT: lui a3, 524288
-; RV32IFD-NEXT: bne s2, a5, .LBB5_2
+; RV32IFD-NEXT: li a4, 1
+; RV32IFD-NEXT: lui a2, 524288
+; RV32IFD-NEXT: bne s0, a4, .LBB5_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: mv a3, a1
+; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB5_2:
-; RV32IFD-NEXT: and a0, a2, a0
-; RV32IFD-NEXT: beqz s0, .LBB5_4
+; RV32IFD-NEXT: lui a1, %hi(.LCPI5_1)
+; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_1)(a1)
+; RV32IFD-NEXT: flt.d a4, fa5, fs0
+; RV32IFD-NEXT: beqz a4, .LBB5_4
; RV32IFD-NEXT: # %bb.3:
-; RV32IFD-NEXT: addi a3, a4, -1
+; RV32IFD-NEXT: addi a2, a3, -1
; RV32IFD-NEXT: .LBB5_4:
-; RV32IFD-NEXT: and a1, a2, a3
-; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: feq.d a1, fs0, fs0
+; RV32IFD-NEXT: neg a3, a1
+; RV32IFD-NEXT: and a1, a3, a2
+; RV32IFD-NEXT: neg a2, a4
+; RV32IFD-NEXT: neg a4, s0
+; RV32IFD-NEXT: and a0, a4, a0
+; RV32IFD-NEXT: or a0, a2, a0
+; RV32IFD-NEXT: and a0, a3, a0
+; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
-; RV32IFD-NEXT: addi sp, sp, 32
+; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_ceil_si64:
@@ -389,46 +373,42 @@ define i64 @test_ceil_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call ceil
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
+; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
+; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
+; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
+; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_0)(a2)
-; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s3, s2
-; RV32IZFINXZDINX-NEXT: call __fixdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_1)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_1+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_1)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s3, a0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a3
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
+; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: li a6, 1
-; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: bne s2, a6, .LBB5_2
+; RV32IZFINXZDINX-NEXT: li a4, 1
+; RV32IZFINXZDINX-NEXT: lui a3, 524288
+; RV32IZFINXZDINX-NEXT: bne ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/84693
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