[llvm] [ARM] Expose supportsTailCalls in ARMTargetTransformInfo (PR #67932)

[Matthew Mirvish via llvm-commits]

https://github.com/mincrmatt12 updated https://github.com/llvm/llvm-project/pull/67932

>From 53783c9b9e2e33d84baf2cb39c52851b8decbbab Mon Sep 17 00:00:00 2001
From: Matthew Mirvish <matthew at mm12.xyz>
Date: Sun, 1 Oct 2023 15:42:12 -0400
Subject: [PATCH] [ARM] Expose supportsTailCalls in ARMTargetTransformInfo

The ARM target doesn't support tail calls on certain older
architectures, however this information is not communicated to the
target transform information. This causes coroutine symmetric transfer
to fail as it adds musttail attributes which throw an assert during
code generation.
---
 llvm/lib/Target/ARM/ARMTargetTransformInfo.h  |  6 ++
 .../Coroutines/coro-split-musttail-armv6.ll   | 60 +++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 llvm/test/Transforms/Coroutines/coro-split-musttail-armv6.ll

diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index bb4b321b530091..d1d699b62e3b24 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -333,6 +333,12 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
 
   bool hasArmWideBranch(bool Thumb) const;
 
+  bool supportsTailCalls() const { return ST->supportsTailCall(); }
+
+  bool supportsTailCallFor(const CallBase *CB) const {
+    return supportsTailCalls();
+  }
+
   /// @}
 };
 
diff --git a/llvm/test/Transforms/Coroutines/coro-split-musttail-armv6.ll b/llvm/test/Transforms/Coroutines/coro-split-musttail-armv6.ll
new file mode 100644
index 00000000000000..3a6b25b8a9ccd9
--- /dev/null
+++ b/llvm/test/Transforms/Coroutines/coro-split-musttail-armv6.ll
@@ -0,0 +1,60 @@
+; Test that ARMv6 correctly masks coroutine infrastructure from generating musttail calls
+; RUN: opt < %s -passes='cgscc(coro-split),simplifycfg,early-cse' -S \
+; RUN:     -mtriple=arm-none-eabi -mcpu=cortex-m0 | FileCheck %s
+
+define void @f() #0 {
+entry:
+  %id = call token @llvm.coro.id(i32 0, ptr null, ptr null, ptr null)
+  %alloc = call ptr @malloc(i64 16) #3
+  %vFrame = call noalias nonnull ptr @llvm.coro.begin(token %id, ptr %alloc)
+
+  %save = call token @llvm.coro.save(ptr null)
+  %addr1 = call ptr @llvm.coro.subfn.addr(ptr null, i8 0)
+  call fastcc void %addr1(ptr null)
+
+  %suspend = call i8 @llvm.coro.suspend(token %save, i1 false)
+  switch i8 %suspend, label %exit [
+    i8 0, label %await.ready
+    i8 1, label %exit
+  ]
+await.ready:
+  %save2 = call token @llvm.coro.save(ptr null)
+  %addr2 = call ptr @llvm.coro.subfn.addr(ptr null, i8 0)
+  call fastcc void %addr2(ptr null)
+
+  %suspend2 = call i8 @llvm.coro.suspend(token %save2, i1 false)
+  switch i8 %suspend2, label %exit [
+    i8 0, label %exit
+    i8 1, label %exit
+  ]
+exit:
+  call i1 @llvm.coro.end(ptr null, i1 false, token none)
+  ret void
+}
+
+; Verify that in the initial function resume is not marked with musttail.
+; CHECK-LABEL: @f(
+; CHECK: %[[addr1:.+]] = call ptr @llvm.coro.subfn.addr(ptr null, i8 0)
+; CHECK-NOT: musttail call fastcc void %[[addr1]](ptr null)
+
+; Verify that ppc target not using PC-Relative addressing in the resume part resume call is not marked with musttail.
+; CHECK-LABEL: @f.resume(
+; CHECK: %[[addr2:.+]] = call ptr @llvm.coro.subfn.addr(ptr null, i8 0)
+; CHECK-NEXT: call fastcc void %[[addr2]](ptr null)
+
+declare token @llvm.coro.id(i32, ptr readnone, ptr nocapture readonly, ptr) #1
+declare i1 @llvm.coro.alloc(token) #2
+declare i64 @llvm.coro.size.i64() #3
+declare ptr @llvm.coro.begin(token, ptr writeonly) #2
+declare token @llvm.coro.save(ptr) #2
+declare ptr @llvm.coro.frame() #3
+declare i8 @llvm.coro.suspend(token, i1) #2
+declare ptr @llvm.coro.free(token, ptr nocapture readonly) #1
+declare i1 @llvm.coro.end(ptr, i1, token) #2
+declare ptr @llvm.coro.subfn.addr(ptr nocapture readonly, i8) #1
+declare ptr @malloc(i64)
+
+attributes #0 = { presplitcoroutine }
+attributes #1 = { argmemonly nounwind readonly }
+attributes #2 = { nounwind }
+attributes #3 = { nounwind readnone }