[llvm] [GISEL] Add G_INSERT_SUBVECTOR and G_EXTRACT_SUBVECTOR (PR #84538)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 9 08:28:07 PST 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/84538
>From 46f38f953c985f09f89674486c263b409425bb45 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 8 Mar 2024 11:04:13 -0800
Subject: [PATCH 1/2] [GISEL] Add G_INSERT_SUBVECTOR and G_EXTRACT_SUBVECTOR
G_INSERT and G_EXTRACT are not sufficient to use to represent both
INSERT/EXTRACT on a subregister and INSERT/EXTRACT on a vector.
We would like to be able to INSERT/EXTRACT on vectors in cases that
INSERT/EXTRACT on vector subregisters are not sufficient, so we add these
opcodes.
---
llvm/docs/GlobalISel/GenericOpcode.rst | 35 +++++++
.../CodeGen/GlobalISel/MachineIRBuilder.h | 19 ++++
llvm/include/llvm/Support/TargetOpcodes.def | 6 ++
llvm/include/llvm/Target/GenericOpcodes.td | 14 +++
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 15 +++
llvm/lib/CodeGen/MachineVerifier.cpp | 98 +++++++++++++++++++
.../GlobalISel/legalizer-info-validation.mir | 6 ++
.../test_g_extract_subvector.mir | 33 +++++++
.../test_g_insert_subvector.mir | 44 +++++++++
9 files changed, 270 insertions(+)
create mode 100644 llvm/test/MachineVerifier/test_g_extract_subvector.mir
create mode 100644 llvm/test/MachineVerifier/test_g_insert_subvector.mir
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index dda367607d0432..f9f9e1186460ee 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -607,6 +607,41 @@ See the LLVM LangRef entry on '``llvm.lround.*'`` for details on behaviour.
Vector Specific Operations
--------------------------
+G_INSERT_SUBVECTOR
+^^^^^^^^^^^^^^^^^^
+
+Insert the second source vector into the first source vector. The index operand
+represents the starting index in the first source vector at which the second
+source vector should be inserted into.
+
+The index must be a constant multiple of the second source vector's minimum
+vector length. If the vectors are scalable, then the index is first scaled by
+the runtime scaling factor. The indices inserted in the source vector must be
+valid indicies of that vector. If this condition cannot be determined statically
+but is false at runtime, then the result vector is undefined.
+
+.. code-block:: none
+
+ %2:_(<vscale x 4 x i64>) = G_INSERT_SUBVECTOR %0:_(<vscale x 4 x i64>), %1:_(<vscale x 2 x i64>), 0
+
+G_EXTRACT_SUBVECTOR
+^^^^^^^^^^^^^^^^^^^
+
+Extract a vector of destination type from the source vector. The index operand
+represents the starting index from which a subvector is extracted from
+the source vector.
+
+The index must be a constant multiple of the source vector's minimum vector
+length. If the source vector is a scalable vector, then the index is first
+scaled by the runtime scaling factor. The indices extracted from the source
+vector must be valid indicies of that vector. If this condition cannot be
+determined statically but is false at runtime, then the result vector is
+undefined.
+
+.. code-block:: none
+
+ %3:_(<vscale x 4 x i64>) = G_EXTRACT_SUBVECTOR %2:_(<vscale x 8 x i64>), 2
+
G_CONCAT_VECTORS
^^^^^^^^^^^^^^^^
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 6762b1b360d5e8..4732eaf4ee27c5 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1121,6 +1121,25 @@ class MachineIRBuilder {
MachineInstrBuilder buildConcatVectors(const DstOp &Res,
ArrayRef<Register> Ops);
+ /// Build and insert `Res = G_INSERT_SUBVECTOR Src0, Src1, Idx`.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res, \p Src0, and \p Src1 must be generic virtual registers with
+ /// vector type.
+ ///
+ /// \return a MachineInstrBuilder for the newly created instruction.
+ MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0,
+ const SrcOp &Src1, unsigned Index);
+
+ /// Build and insert `Res = G_EXTRACT_SUBVECTOR Src, Idx0`.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res and \p Src must be generic virtual registers with vector type.
+ ///
+ /// \return a MachineInstrBuilder for the newly created instruction.
+ MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src,
+ unsigned Index);
+
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
const SrcOp &Op, unsigned Index);
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 94fba491148b2e..3dade14f043b60 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -727,6 +727,12 @@ HANDLE_TARGET_OPCODE(G_BR)
/// Generic branch to jump table entry.
HANDLE_TARGET_OPCODE(G_BRJT)
+/// Generic insert subvector.
+HANDLE_TARGET_OPCODE(G_INSERT_SUBVECTOR)
+
+/// Generic extract subvector.
+HANDLE_TARGET_OPCODE(G_EXTRACT_SUBVECTOR)
+
/// Generic insertelement.
HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index d967885aa2d758..8dc84fb0ba0524 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1426,6 +1426,20 @@ def G_WRITE_REGISTER : GenericInstruction {
// Vector ops
//------------------------------------------------------------------------------
+// Generic insert subvector.
+def G_INSERT_SUBVECTOR : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type1:$src1, untyped_imm_0:$idx);
+ let hasSideEffects = false;
+}
+
+// Generic extract subvector.
+def G_EXTRACT_SUBVECTOR : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src, untyped_imm_0:$idx);
+ let hasSideEffects = false;
+}
+
// Generic insertelement.
def G_INSERT_VECTOR_ELT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 28e5bf85ca9ce6..9b12d443c96e98 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -877,6 +877,21 @@ MachineIRBuilder::buildSelect(const DstOp &Res, const SrcOp &Tst,
return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
}
+MachineInstrBuilder MachineIRBuilder::buildInsertSubvector(const DstOp &Res,
+ const SrcOp &Src0,
+ const SrcOp &Src1,
+ unsigned Idx) {
+ return buildInstr(TargetOpcode::G_INSERT_SUBVECTOR, Res,
+ {Src0, Src1, uint64_t(Idx)});
+}
+
+MachineInstrBuilder MachineIRBuilder::buildExtractSubvector(const DstOp &Res,
+ const SrcOp &Src,
+ unsigned Idx) {
+ return buildInstr(TargetOpcode::G_INSERT_SUBVECTOR, Res,
+ {Src, uint64_t(Idx)});
+}
+
MachineInstrBuilder
MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
const SrcOp &Elt, const SrcOp &Idx) {
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index ecb3bd33bdfd49..7041dc868cb917 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1603,6 +1603,104 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
report("G_BSWAP size must be a multiple of 16 bits", MI);
break;
}
+ case TargetOpcode::G_INSERT_SUBVECTOR: {
+ const MachineOperand &Src0Op = MI->getOperand(1);
+ if (!Src0Op.isReg()) {
+ report("G_INSERT_SUBVECTOR first source must be a register", MI);
+ break;
+ }
+
+ const MachineOperand &Src1Op = MI->getOperand(2);
+ if (!Src1Op.isReg()) {
+ report("G_INSERT_SUBVECTOR second source must be a register", MI);
+ break;
+ }
+
+ const MachineOperand &IndexOp = MI->getOperand(3);
+ if (!IndexOp.isImm()) {
+ report("G_INSERT_SUBVECTOR index must be an immediate", MI);
+ break;
+ }
+
+ LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+ LLT Src0Ty = MRI->getType(Src0Op.getReg());
+ LLT Src1Ty = MRI->getType(Src1Op.getReg());
+
+ if (!DstTy.isVector()) {
+ report("Destination type must be a vector", MI);
+ break;
+ }
+
+ if (!Src0Ty.isVector()) {
+ report("First source must be a vector", MI);
+ break;
+ }
+
+ if (!Src1Ty.isVector()) {
+ report("Second source must be a vector", MI);
+ break;
+ }
+
+ if (DstTy != Src0Ty) {
+ report("Destination type must match the first source vector type", MI);
+ break;
+ }
+
+ if (Src0Ty.getElementType() != Src1Ty.getElementType()) {
+ report("Element type of source vectors must be the same", MI);
+ break;
+ }
+
+ if (IndexOp.getImm() != 0 &&
+ Src1Ty.getElementCount().getKnownMinValue() % IndexOp.getImm() != 0) {
+ report("Index must be a multiple of the second source vector's "
+ "minimum vector length",
+ MI);
+ break;
+ }
+ break;
+ }
+ case TargetOpcode::G_EXTRACT_SUBVECTOR: {
+ const MachineOperand &SrcOp = MI->getOperand(1);
+ if (!SrcOp.isReg()) {
+ report("G_EXTRACT_SUBVECTOR first source must be a register", MI);
+ break;
+ }
+
+ const MachineOperand &IndexOp = MI->getOperand(2);
+ if (!IndexOp.isImm()) {
+ report("G_EXTRACT_SUBVECTOR index must be an immediate", MI);
+ break;
+ }
+
+ LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+ LLT SrcTy = MRI->getType(SrcOp.getReg());
+
+ if (!DstTy.isVector()) {
+ report("Destination type must be a vector", MI);
+ break;
+ }
+
+ if (!SrcTy.isVector()) {
+ report("First source must be a vector", MI);
+ break;
+ }
+
+ if (DstTy.getElementType() != SrcTy.getElementType()) {
+ report("Element type of vectors must be the same", MI);
+ break;
+ }
+
+ if (IndexOp.getImm() != 0 &&
+ SrcTy.getElementCount().getKnownMinValue() % IndexOp.getImm() != 0) {
+ report("Index must be a multiple of the source vector's minimum vector "
+ "length",
+ MI);
+ break;
+ }
+
+ break;
+ }
case TargetOpcode::G_SHUFFLE_VECTOR: {
const MachineOperand &MaskOp = MI->getOperand(3);
if (!MaskOp.isShuffleMask()) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index ecad3f11513487..ac330918b430a0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -616,6 +616,12 @@
# DEBUG-NEXT: G_BRJT (opcode {{[0-9]+}}): 2 type indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_INSERT_SUBVECTOR (opcode {{[0-9]+}}): 2 type indices, 1 imm index
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_EXTRACT_SUBVECTOR (opcode {{[0-9]+}}): 1 type index, 1 imm index
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_INSERT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/MachineVerifier/test_g_extract_subvector.mir b/llvm/test/MachineVerifier/test_g_extract_subvector.mir
new file mode 100644
index 00000000000000..9ea54dfb981554
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_g_extract_subvector.mir
@@ -0,0 +1,33 @@
+# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name: g_extract_subvector
+tracksRegLiveness: true
+liveins:
+body: |
+ bb.0:
+ %0:_(s32) = G_CONSTANT i32 0
+ %1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ %2:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+
+ ; CHECK: G_EXTRACT_SUBVECTOR first source must be a register
+ %3:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR 1, 0
+
+ ; CHECK: G_EXTRACT_SUBVECTOR index must be an immediate
+ %4:_(<vscale x 1 x s32>) = G_EXTRACT_SUBVECTOR %2, %0
+
+ ; CHECK: Destination type must be a vector
+ %5:_(s32) = G_EXTRACT_SUBVECTOR %2, 0
+
+ ; CHECK: First source must be a vector
+ %6:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR %0, 0
+
+ %7:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+
+ ; CHECK: Element type of vectors must be the same
+ %8:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR %7, 0
+
+ ; CHECK: Index must be a multiple of the source vector's minimum vector length
+ %9:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR %1, 3
+...
diff --git a/llvm/test/MachineVerifier/test_g_insert_subvector.mir b/llvm/test/MachineVerifier/test_g_insert_subvector.mir
new file mode 100644
index 00000000000000..5f26313b985319
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_g_insert_subvector.mir
@@ -0,0 +1,44 @@
+# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name: g_splat_vector
+tracksRegLiveness: true
+liveins:
+body: |
+ bb.0:
+ %0:_(s32) = G_CONSTANT i32 0
+ %1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ %2:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+
+ ; CHECK: G_INSERT_SUBVECTOR first source must be a register
+ %3:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR 1, %2, 0
+
+ ; CHECK: G_INSERT_SUBVECTOR second source must be a register
+ %4:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR %1, 1, 0
+
+ ; CHECK: G_INSERT_SUBVECTOR index must be an immediate
+ %5:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR %1, %2, %0
+
+ ; CHECK: Destination type must be a vector
+ %6:_(s32) = G_INSERT_SUBVECTOR %1, %2, 0
+
+ ; CHECK: First source must be a vector
+ %7:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR %0, %2, 0
+
+ ; CHECK: Second source must be a vector
+ %8:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR %1, %0, 0
+
+ ; CHECK: Destination type must match the first source vector type
+ %9:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR %2, %1, 0
+
+ %10:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+
+ ; CHECK: Element type of source vectors must be the same
+ %11:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR %1, %10, 0
+
+ %12:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
+
+ ; CHECK: Index must be a multiple of the second source vector's minimum vector length
+ %13:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR %12, %1, 3
+...
>From e6d63018f97388bfd4b723a4b567071a65002ccd Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Sat, 9 Mar 2024 08:27:04 -0800
Subject: [PATCH 2/2] fixup! remove requires
---
llvm/test/MachineVerifier/test_g_extract_subvector.mir | 4 +---
llvm/test/MachineVerifier/test_g_insert_subvector.mir | 3 +--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/llvm/test/MachineVerifier/test_g_extract_subvector.mir b/llvm/test/MachineVerifier/test_g_extract_subvector.mir
index 9ea54dfb981554..bc167d2eb7bcdb 100644
--- a/llvm/test/MachineVerifier/test_g_extract_subvector.mir
+++ b/llvm/test/MachineVerifier/test_g_extract_subvector.mir
@@ -1,6 +1,4 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
-# REQUIRES: aarch64-registered-target
-
+# RUN: not --crash llc -o - -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
---
name: g_extract_subvector
tracksRegLiveness: true
diff --git a/llvm/test/MachineVerifier/test_g_insert_subvector.mir b/llvm/test/MachineVerifier/test_g_insert_subvector.mir
index 5f26313b985319..dce30cdb6b1e55 100644
--- a/llvm/test/MachineVerifier/test_g_insert_subvector.mir
+++ b/llvm/test/MachineVerifier/test_g_insert_subvector.mir
@@ -1,5 +1,4 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
-# REQUIRES: aarch64-registered-target
+# RUN: not --crash llc -o - -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
---
name: g_splat_vector
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