[llvm] [RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s [nfc] (PR #84563)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 8 12:43:18 PST 2024
https://github.com/preames created https://github.com/llvm/llvm-project/pull/84563
The prior naming scheme is incredibly hard to make sense out of. I suspect the usage was actually backwards from intent - though that didn't matter for any in tree schedule model.
>From fb971e38b0c11931bd6e4d2735c12b87d006aff8 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Fri, 8 Mar 2024 12:33:37 -0800
Subject: [PATCH] [RISCV] Rename schedule classes for vmv.s.x, vmv.x.s,
vfmv.s.f, and vfmv.f.s [nfc]
The prior naming scheme is increadible hard to make sense out of. I suspect
the usage was actually backwards from intent - though that didn't matter for
any in tree schedule model.
---
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 8 ++--
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 8 ++--
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 20 ++++-----
llvm/lib/Target/RISCV/RISCVScheduleV.td | 42 +++++++++----------
4 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index d2d824da9c7831..d7807c12037807 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1637,11 +1637,11 @@ def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
let vm = 1, RVVConstraint = NoConstraint in {
def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
(ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
- Sched<[WriteVIMovVX, ReadVIMovVX]>;
+ Sched<[WriteVMovXS, ReadVMovXS]>;
let Constraints = "$vd = $vd_wb" in
def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb),
(ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
- Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
+ Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@@ -1655,11 +1655,11 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
// Floating-Point Scalar Move Instructions
def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
(ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
- Sched<[WriteVFMovVF, ReadVFMovVF]>;
+ Sched<[WriteVMovFS, ReadVMovFS]>;
let Constraints = "$vd = $vd_wb" in
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb),
(ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
- Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>;
+ Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 48cf48e8af58fb..ae93bf69487565 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -6767,14 +6767,14 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S:
Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>,
- Sched<[WriteVIMovVX, ReadVIMovVX]>,
+ Sched<[WriteVMovXS, ReadVMovXS]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
Constraints = "$rd = $rs1" in
def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
(ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),
[]>,
- Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
+ Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>,
RISCVVPseudo;
}
} // Predicates = [HasVInstructions]
@@ -6793,7 +6793,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
def "PseudoVFMV_" # f.FX # "_S_" # mx :
Pseudo<(outs f.fprclass:$rd),
(ins m.vrclass:$rs2, ixlenimm:$sew), []>,
- Sched<[WriteVFMovVF, ReadVFMovVF]>,
+ Sched<[WriteVMovFS, ReadVMovFS]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
Constraints = "$rd = $rs1" in
@@ -6802,7 +6802,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
(ins m.vrclass:$rs1, f.fprclass:$rs2,
AVL:$vl, ixlenimm:$sew),
[]>,
- Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>,
+ Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>,
RISCVVPseudo;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index b21a56bdcdd20a..240d170bfcf6f9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -887,10 +887,10 @@ foreach mx = SchedMxList in {
// 16. Vector Permutation Instructions
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 1)] in {
- def : WriteRes<WriteVIMovVX, [SiFive7VCQ, SiFive7VA]>;
- def : WriteRes<WriteVIMovXV, [SiFive7VCQ, SiFive7VA]>;
- def : WriteRes<WriteVFMovVF, [SiFive7VCQ, SiFive7VA]>;
- def : WriteRes<WriteVFMovFV, [SiFive7VCQ, SiFive7VA]>;
+ def : WriteRes<WriteVMovSX, [SiFive7VCQ, SiFive7VA]>;
+ def : WriteRes<WriteVMovXS, [SiFive7VCQ, SiFive7VA]>;
+ def : WriteRes<WriteVMovSF, [SiFive7VCQ, SiFive7VA]>;
+ def : WriteRes<WriteVMovFS, [SiFive7VCQ, SiFive7VA]>;
}
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
@@ -1190,12 +1190,12 @@ defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
// 17. Vector Permutation Instructions
-def : ReadAdvance<ReadVIMovVX, 0>;
-def : ReadAdvance<ReadVIMovXV, 0>;
-def : ReadAdvance<ReadVIMovXX, 0>;
-def : ReadAdvance<ReadVFMovVF, 0>;
-def : ReadAdvance<ReadVFMovFV, 0>;
-def : ReadAdvance<ReadVFMovFX, 0>;
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 0be681de3daf69..379622d4ca834c 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -196,7 +196,7 @@ multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes
// by the ReadAdvance. For example:
// ```
// defm "" : LMULReadAdvance<"ReadVIALUX", 1,
-// LMULSchedWriteList<["WriteVIMovVX"]>.value>;
+// LMULSchedWriteList<["WriteVMovSX"]>.value>;
// ```
class LMULSchedWriteListImpl<list<string> names, list<string> MxList> {
list<SchedWrite> value = !foldl([]<SchedWrite>,
@@ -484,11 +484,11 @@ defm "" : LMULSchedWrites<"WriteVIdxV">;
// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
-def WriteVIMovVX : SchedWrite;
-def WriteVIMovXV : SchedWrite;
+def WriteVMovSX : SchedWrite;
+def WriteVMovXS : SchedWrite;
// 16.2. Floating-Point Scalar Move Instructions
-def WriteVFMovVF : SchedWrite;
-def WriteVFMovFV : SchedWrite;
+def WriteVMovSF : SchedWrite;
+def WriteVMovFS : SchedWrite;
// 16.3. Vector Slide Instructions
defm "" : LMULSchedWrites<"WriteVISlideX">;
defm "" : LMULSchedWrites<"WriteVISlideI">;
@@ -709,13 +709,13 @@ defm "" : LMULSchedReads<"ReadVIotaV">;
// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
-def ReadVIMovVX : SchedRead;
-def ReadVIMovXV : SchedRead;
-def ReadVIMovXX : SchedRead;
+def ReadVMovXS : SchedRead;
+def ReadVMovSX_V : SchedRead;
+def ReadVMovSX_X : SchedRead;
// 16.2. Floating-Point Scalar Move Instructions
-def ReadVFMovVF : SchedRead;
-def ReadVFMovFV : SchedRead;
-def ReadVFMovFX : SchedRead;
+def ReadVMovFS : SchedRead;
+def ReadVMovSF_V : SchedRead;
+def ReadVMovSF_F : SchedRead;
// 16.3. Vector Slide Instructions
defm "" : LMULSchedReads<"ReadVISlideV">;
defm "" : LMULSchedReads<"ReadVISlideX">;
@@ -921,10 +921,10 @@ defm "" : LMULWriteRes<"WriteVIotaV", []>;
defm "" : LMULWriteRes<"WriteVIdxV", []>;
// 16. Vector Permutation Instructions
-def : WriteRes<WriteVIMovVX, []>;
-def : WriteRes<WriteVIMovXV, []>;
-def : WriteRes<WriteVFMovVF, []>;
-def : WriteRes<WriteVFMovFV, []>;
+def : WriteRes<WriteVMovSX, []>;
+def : WriteRes<WriteVMovXS, []>;
+def : WriteRes<WriteVMovSF, []>;
+def : WriteRes<WriteVMovFS, []>;
defm "" : LMULWriteRes<"WriteVISlideX", []>;
defm "" : LMULWriteRes<"WriteVISlideI", []>;
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
@@ -1082,12 +1082,12 @@ defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
// 16. Vector Permutation Instructions
-def : ReadAdvance<ReadVIMovVX, 0>;
-def : ReadAdvance<ReadVIMovXV, 0>;
-def : ReadAdvance<ReadVIMovXX, 0>;
-def : ReadAdvance<ReadVFMovVF, 0>;
-def : ReadAdvance<ReadVFMovFV, 0>;
-def : ReadAdvance<ReadVFMovFX, 0>;
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
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