[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Alfie Richards via llvm-commits]

AlfieRichardsArm wrote:

> > Looks like the test failures were coming from ambiguous matchables being sorted differently.
> 
> Why were they sorted differently?

They were ambiguous matchables so didnt have any inherent order. 
On my machine after the stable sort the relevant matchables ended up in different orders on a debug build vs a release build, so I would guess there was some randomness involved.

I'm not certain why this wouldn't have come up before but my guess is that adding `preferSmallerInstructions` causes some instability which wasn't present before. Either way I think https://github.com/llvm/llvm-project/pull/84483 is the correct solution. It makes sense (to me) for there to be multiple of the same instruction but with different feature requirements and that they should have an ordering applied to them.

https://github.com/llvm/llvm-project/pull/83436