[llvm] [TTI][RISCV]Improve costs for whole vector reg extract/insert. (PR #80164)

[Luke Lau via llvm-commits]

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@@ -457,12 +457,28 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     // vslidedown.vi  v8, v9, 2
     return LT.first *
            getRISCVInstructionCost(RISCV::VSLIDEDOWN_VI, LT.second, CostKind);
-  case TTI::SK_InsertSubvector:
+  case TTI::SK_InsertSubvector: {
+    if (Index == 0 && !Args.empty() && any_of(Args, UndefValue::classof))
+      return TTI::TCC_Free;
+    const unsigned MinVLen = ST->getRealMinVLen();
+    const unsigned MaxVLen = ST->getRealMaxVLen();
+    // Whole vector insert - just the vector itself.
+    if (auto *FSubTy = dyn_cast<FixedVectorType>(SubTp);
+        FSubTy && Index == 0 && MinVLen == MaxVLen) {
+      unsigned TpRegs = getRegUsageForType(Tp);
+      unsigned SubTpRegs = getRegUsageForType(SubTp);
+      unsigned NextSubTpRegs = getRegUsageForType(FixedVectorType::get(
+          Tp->getElementType(), FSubTy->getNumElements() + 1));
+      if (SubTpRegs != 0 && SubTpRegs != NextSubTpRegs && TpRegs >= SubTpRegs)
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lukel97 wrote:

Is it possible for `TpRegs < SubTpRegs`?

https://github.com/llvm/llvm-project/pull/80164