[llvm] a110a1c - [AArch64] MachineCombiner msub matching for i64

[via llvm-commits]

Author: zhongyunde 00443407
Date: 2024-03-08T18:14:26+08:00
New Revision: a110a1c0ed9850be168cd0e29f05179e80941b04

URL: https://github.com/llvm/llvm-project/commit/a110a1c0ed9850be168cd0e29f05179e80941b04
DIFF: https://github.com/llvm/llvm-project/commit/a110a1c0ed9850be168cd0e29f05179e80941b04.diff

LOG: [AArch64] MachineCombiner msub matching for i64

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    llvm/test/CodeGen/AArch64/scalar-mla-mls.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 5893f76dbd5544..02943b8a4ab158 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -6114,8 +6114,8 @@ static bool getMaddPatterns(MachineInstr &Root,
     setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULSUBW_OP1);
     break;
   case AArch64::SUBXrr:
-    setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBX_OP1);
     setFound(AArch64::MADDXrrr, 2, AArch64::XZR, MCP::MULSUBX_OP2);
+    setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBX_OP1);
     break;
   case AArch64::ADDWri:
     setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULADDWI_OP1);

diff  --git a/llvm/test/CodeGen/AArch64/scalar-mla-mls.ll b/llvm/test/CodeGen/AArch64/scalar-mla-mls.ll
index 36ac36701fa8aa..c8ba50ae0cc3ca 100644
--- a/llvm/test/CodeGen/AArch64/scalar-mla-mls.ll
+++ b/llvm/test/CodeGen/AArch64/scalar-mla-mls.ll
@@ -29,3 +29,35 @@ entry:
   store i32 %sub, ptr %a, align 4
   ret ptr %a
 }
+
+define ptr @test_scalar_msub_i64(ptr %a, ptr %b) {
+; CHECK-LABEL: test_scalar_msub_i64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ldr x8, [x1]
+; CHECK-NEXT:    ldur x9, [x0, #4]
+; CHECK-NEXT:    ldr x10, [x0]
+; CHECK-NEXT:    ldur x12, [x1, #4]
+; CHECK-NEXT:    mul x11, x9, x8
+; CHECK-NEXT:    mul x8, x8, x10
+; CHECK-NEXT:    madd x10, x12, x10, x11
+; CHECK-NEXT:    msub x8, x12, x9, x8
+; CHECK-NEXT:    stur x10, [x0, #4]
+; CHECK-NEXT:    str x8, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = load i64, ptr %a, align 8
+  %1 = load i64, ptr %b, align 8
+  %mul = mul nsw i64 %1, %0
+  %_M_imag = getelementptr inbounds i8, ptr %a, i64 4
+  %2 = load i64, ptr %_M_imag, align 8
+  %_M_imag.i = getelementptr inbounds i8, ptr %b, i64 4
+  %3 = load i64, ptr %_M_imag.i, align 8
+  %mul3 = mul nsw i64 %3, %2
+  %sub = sub nsw i64 %mul, %mul3
+  %mul6 = mul nsw i64 %3, %0
+  %mul9 = mul nsw i64 %2, %1
+  %add = add nsw i64 %mul6, %mul9
+  store i64 %add, ptr %_M_imag, align 8
+  store i64 %sub, ptr %a, align 8
+  ret ptr %a
+}