[llvm] [llvm][mc][riscv] MC support of T-Head vector extension (xtheadvector) (PR #84447)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 8 01:29:27 PST 2024
https://github.com/kata-ark updated https://github.com/llvm/llvm-project/pull/84447
>From 544e7d4207c28eabeab3bb5d324c0f202582c9c1 Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Mon, 26 Feb 2024 15:09:08 +0800
Subject: [PATCH 1/9] add t-head vector definitions
---
.../llvm/TargetParser/RISCVTargetParser.h | 14 +
llvm/lib/Support/RISCVISAInfo.cpp | 33 +-
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 85 +-
.../RISCV/Disassembler/RISCVDisassembler.cpp | 2 +
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
.../RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 15 +
.../RISCV/MCTargetDesc/RISCVInstPrinter.h | 2 +
llvm/lib/Target/RISCV/RISCV.td | 7 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 33 +
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
.../lib/Target/RISCV/RISCVInstrInfoXTHeadV.td | 750 ++++
llvm/lib/TargetParser/RISCVTargetParser.cpp | 28 +
llvm/test/MC/RISCV/attribute-arch.s | 12 +
llvm/test/MC/RISCV/xtheadvector/add.s | 306 ++
llvm/test/MC/RISCV/xtheadvector/and.s | 42 +
llvm/test/MC/RISCV/xtheadvector/clip.s | 78 +
llvm/test/MC/RISCV/xtheadvector/compare.s | 253 ++
llvm/test/MC/RISCV/xtheadvector/convert.s | 186 +
llvm/test/MC/RISCV/xtheadvector/div.s | 105 +
llvm/test/MC/RISCV/xtheadvector/fadd.s | 84 +
llvm/test/MC/RISCV/xtheadvector/fcompare.s | 162 +
llvm/test/MC/RISCV/xtheadvector/fdiv.s | 48 +
llvm/test/MC/RISCV/xtheadvector/fminmax.s | 60 +
llvm/test/MC/RISCV/xtheadvector/fmul.s | 60 +
llvm/test/MC/RISCV/xtheadvector/fmv.s | 30 +
llvm/test/MC/RISCV/xtheadvector/fothers.s | 40 +
llvm/test/MC/RISCV/xtheadvector/freduction.s | 90 +
llvm/test/MC/RISCV/xtheadvector/fsub.s | 96 +
llvm/test/MC/RISCV/xtheadvector/load.s | 345 ++
llvm/test/MC/RISCV/xtheadvector/mask.s | 141 +
llvm/test/MC/RISCV/xtheadvector/minmax.s | 105 +
llvm/test/MC/RISCV/xtheadvector/mul.s | 201 +
llvm/test/MC/RISCV/xtheadvector/mv.s | 36 +
llvm/test/MC/RISCV/xtheadvector/or.s | 42 +
llvm/test/MC/RISCV/xtheadvector/others.s | 138 +
llvm/test/MC/RISCV/xtheadvector/reduction.s | 135 +
llvm/test/MC/RISCV/xtheadvector/shift.s | 264 ++
.../MC/RISCV/xtheadvector/sign-injection.s | 84 +
llvm/test/MC/RISCV/xtheadvector/store.s | 201 +
llvm/test/MC/RISCV/xtheadvector/sub.s | 270 ++
.../MC/RISCV/xtheadvector/vsetvl-invaild.s | 15 +
llvm/test/MC/RISCV/xtheadvector/vsetvl.s | 118 +
llvm/test/MC/RISCV/xtheadvector/xor.s | 42 +
llvm/test/MC/RISCV/xtheadvector/zvlsseg.s | 3370 +++++++++++++++++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 6 +
46 files changed, 8130 insertions(+), 7 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
create mode 100644 llvm/test/MC/RISCV/xtheadvector/add.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/and.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/clip.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/compare.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/convert.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/div.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fadd.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fcompare.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fdiv.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fminmax.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fmul.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fmv.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fothers.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/freduction.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fsub.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/load.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/mask.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/minmax.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/mul.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/mv.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/or.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/others.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/reduction.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/shift.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/sign-injection.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/store.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/sub.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/vsetvl-invaild.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/vsetvl.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/xor.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/zvlsseg.s
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index cdd19189f8dc7d..36ec58ea3469c1 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -69,9 +69,16 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
}
+// Is this a EDIV value that can be encoded into the VTYPE format.
+inline static bool isValidEDIV(unsigned EDIV) {
+ return isPowerOf2_32(EDIV) && EDIV <= 8;
+}
+
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
bool MaskAgnostic);
+unsigned encodeXTHeadVTYPE(unsigned SEW, unsigned LMUL, unsigned EDIV);
+
inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
unsigned VLMUL = VType & 0x7;
return static_cast<RISCVII::VLMUL>(VLMUL);
@@ -101,12 +108,19 @@ inline static unsigned getSEW(unsigned VType) {
return decodeVSEW(VSEW);
}
+inline static unsigned encodeEDIV(unsigned EDIV) {
+ assert(isValidEDIV(EDIV) && "Unexpected EDIV value");
+ return Log2_32(EDIV);
+}
+
inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
void printVType(unsigned VType, raw_ostream &OS);
+void printXTHeadVType(unsigned VType, raw_ostream &OS);
+
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
std::optional<RISCVII::VLMUL>
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 6eec03fd6f7082..f8f8b152c20eca 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -106,6 +106,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadmempair", {1, 0}},
{"xtheadsync", {1, 0}},
{"xtheadvdot", {1, 0}},
+ {"xtheadvector", {1, 0}},
+ {"xtheadzvamo", {1, 0}},
{"xventanacondops", {1, 0}},
{"za128rs", {1, 0}},
@@ -368,6 +370,18 @@ static StringRef getExtensionType(StringRef Ext) {
return StringRef();
}
+static const RISCVSupportedExtension *
+findExtensionIn(llvm::ArrayRef<RISCVSupportedExtension> ExtensionInfos,
+ StringRef Ext, unsigned MajorVersion, unsigned MinorVersion) {
+ auto Range = std::equal_range(ExtensionInfos.begin(), ExtensionInfos.end(),
+ Ext, LessExtName());
+ for (auto I = Range.first, E = Range.second; I != E; ++I)
+ if (I->Version.Major == MajorVersion && I->Version.Minor == MinorVersion) {
+ return I;
+ }
+ return ExtensionInfos.end();
+}
+
static std::optional<RISCVISAInfo::ExtensionVersion>
isExperimentalExtension(StringRef Ext) {
auto I =
@@ -406,11 +420,8 @@ bool RISCVISAInfo::isSupportedExtension(StringRef Ext, unsigned MajorVersion,
unsigned MinorVersion) {
for (auto ExtInfo : {ArrayRef(SupportedExtensions),
ArrayRef(SupportedExperimentalExtensions)}) {
- auto Range =
- std::equal_range(ExtInfo.begin(), ExtInfo.end(), Ext, LessExtName());
- for (auto I = Range.first, E = Range.second; I != E; ++I)
- if (I->Version.Major == MajorVersion && I->Version.Minor == MinorVersion)
- return true;
+ return findExtensionIn(ExtInfo, Ext, MajorVersion, MinorVersion) !=
+ ExtInfo.end();
}
return false;
@@ -1038,6 +1049,16 @@ Error RISCVISAInfo::checkDependency() {
return createStringError(errc::invalid_argument,
"'zcf' is only supported for 'rv32'");
+ if (Exts.count("xtheadzvamo") && !Exts.count("a"))
+ return createStringError(
+ errc::invalid_argument,
+ "'xtheadzvamo' requires 'a' extension to also be specified");
+
+ if (Exts.count("xtheadvector") && HasVector)
+ return createStringError(
+ errc::invalid_argument,
+ "'xtheadvector' extension is incompatible with 'v' or 'zve*' extension");
+
return Error::success();
}
@@ -1045,6 +1066,7 @@ static const char *ImpliedExtsD[] = {"f"};
static const char *ImpliedExtsF[] = {"zicsr"};
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
static const char *ImpliedExtsXTHeadVdot[] = {"v"};
+static const char *ImpliedExtsXTHeadZvamo[] = {"a"};
static const char *ImpliedExtsXSfvcp[] = {"zve32x"};
static const char *ImpliedExtsXSfvfnrclipxfqf[] = {"zve32f"};
static const char *ImpliedExtsXSfvfwmaccqqq[] = {"zvfbfmin"};
@@ -1125,6 +1147,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"xsfvqmaccdod"}, {ImpliedExtsXSfvqmaccdod}},
{{"xsfvqmaccqoq"}, {ImpliedExtsXSfvqmaccqoq}},
{{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
+ {{"xtheadzvamo"}, {ImpliedExtsXTHeadZvamo}},
{{"zabha"}, {ImpliedExtsZabha}},
{{"zacas"}, {ImpliedExtsZacas}},
{{"zcb"}, {ImpliedExtsZcb}},
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d83979a873f2a3..920009ab72baa9 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -201,6 +201,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
ParseStatus parsePseudoJumpSymbol(OperandVector &Operands);
ParseStatus parseJALOffset(OperandVector &Operands);
ParseStatus parseVTypeI(OperandVector &Operands);
+ ParseStatus parseXTHeadVTypeI(OperandVector &Operands);
ParseStatus parseMaskReg(OperandVector &Operands);
ParseStatus parseInsnDirectiveOpcode(OperandVector &Operands);
ParseStatus parseInsnCDirectiveOpcode(OperandVector &Operands);
@@ -329,6 +330,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
FPImmediate,
SystemRegister,
VType,
+ XTHeadVType,
FRM,
Fence,
Rlist,
@@ -422,6 +424,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
SysReg = o.SysReg;
break;
case KindTy::VType:
+ case KindTy::XTHeadVType:
VType = o.VType;
break;
case KindTy::FRM:
@@ -588,6 +591,11 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return isVTypeImm(11);
return Kind == KindTy::VType;
}
+ bool isXTHeadVTypeI() const {
+ if (Kind == KindTy::Immediate)
+ return isVTypeImm(11);
+ return Kind == KindTy::XTHeadVType;
+ }
/// Return true if the operand is a valid for the fence instruction e.g.
/// ('iorw').
@@ -1002,7 +1010,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
}
unsigned getVType() const {
- assert(Kind == KindTy::VType && "Invalid type access!");
+ assert((Kind == KindTy::VType || Kind == KindTy::XTHeadVType) &&
+ "Invalid type access!");
return VType.Val;
}
@@ -1044,6 +1053,11 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVVType::printVType(getVType(), OS);
OS << '>';
break;
+ case KindTy::XTHeadVType:
+ OS << "<vtype: ";
+ RISCVVType::printXTHeadVType(getVType(), OS);
+ OS << '>';
+ break;
case KindTy::FRM:
OS << "<frm: ";
roundingModeToString(getFRM());
@@ -1168,6 +1182,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return Op;
}
+ static std::unique_ptr<RISCVOperand> createXTHeadVType(unsigned VTypeI, SMLoc S) {
+ auto Op = std::make_unique<RISCVOperand>(KindTy::XTHeadVType);
+ Op->VType.Val = VTypeI;
+ Op->StartLoc = S;
+ Op->EndLoc = S;
+ return Op;
+ }
+
static void addExpr(MCInst &Inst, const MCExpr *Expr, bool IsRV64Imm) {
assert(Expr && "Expr shouldn't be null!");
int64_t Imm = 0;
@@ -1363,9 +1385,10 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
bool MatchingInlineAsm) {
MCInst Inst;
FeatureBitset MissingFeatures;
+ bool IsRVV0p71 = getSTI().hasFeature(RISCV::FeatureVendorXTHeadV);
auto Result = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
- MatchingInlineAsm);
+ MatchingInlineAsm, IsRVV0p71 ? 1 : 0);
switch (Result) {
default:
break;
@@ -1592,6 +1615,13 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return generateVTypeError(ErrorLoc);
}
+ case Match_InvalidXTHeadVTypeI: {
+ SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+ return Error(
+ ErrorLoc,
+ "operand must be "
+ "e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|8] for RVV0.71");
+ }
case Match_InvalidVMaskRegister: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(ErrorLoc, "operand must be v0.t");
@@ -2225,6 +2255,57 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
"e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
}
+ParseStatus RISCVAsmParser::parseXTHeadVTypeI(OperandVector &Operands) {
+ SMLoc S = getLoc();
+ if (getLexer().isNot(AsmToken::Identifier))
+ return ParseStatus::NoMatch;
+
+ SmallVector<AsmToken, 7> VTypeIElements;
+ auto MatchFail = [&]() {
+ while (!VTypeIElements.empty())
+ getLexer().UnLex(VTypeIElements.pop_back_val());
+ return ParseStatus::NoMatch;
+ };
+
+ // Put all the tokens for vtypei operand into VTypeIElements vector.
+ while (getLexer().isNot(AsmToken::EndOfStatement)) {
+ VTypeIElements.push_back(getLexer().getTok());
+ getLexer().Lex();
+ if (getLexer().is(AsmToken::EndOfStatement))
+ break;
+ if (getLexer().isNot(AsmToken::Comma))
+ return MatchFail();
+ AsmToken Comma = getLexer().getTok();
+ VTypeIElements.push_back(Comma);
+ getLexer().Lex();
+ }
+
+ if (VTypeIElements.size() == 5) {
+ // The VTypeIElements layout is:
+ // SEW comma LMUL comma EDIV
+ // 0 1 2 3 4
+ StringRef Prefix[] = {"e", "m", "d"};
+ unsigned VTypeEle[3];
+ for (size_t i = 0; i < 3; ++i) {
+ StringRef Name = VTypeIElements[2 * i].getIdentifier();
+ if (!Name.consume_front(Prefix[i]) || Name.getAsInteger(10, VTypeEle[i]))
+ return MatchFail();
+ }
+
+ if (!RISCVVType::isValidSEW(VTypeEle[0]) ||
+ !RISCVVType::isValidLMUL(VTypeEle[1], false) ||
+ !RISCVVType::isValidEDIV(VTypeEle[2]))
+ return MatchFail();
+
+ unsigned VTypeI =
+ RISCVVType::encodeXTHeadVTYPE(VTypeEle[0], VTypeEle[1], VTypeEle[2]);
+ Operands.push_back(RISCVOperand::createXTHeadVType(VTypeI, S));
+ return ParseStatus::Success;
+ }
+
+ return MatchFail();
+}
+
ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
if (getLexer().isNot(AsmToken::Identifier))
return ParseStatus::NoMatch;
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index f1ca1212ec378e..fe636a2bdd2e2f 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -581,6 +581,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"XTHeadSync custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
"XTHeadVdot custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV, DecoderTableRVV0p7132,
+ "XTHeadV custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custom opcode table");
TRY_TO_DECODE_FEATURE(
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 6d0381c30d3e86..b7ee9817dc94c5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -293,6 +293,7 @@ enum OperandType : unsigned {
OPERAND_CLUI_IMM,
OPERAND_VTYPEI10,
OPERAND_VTYPEI11,
+ OPERAND_XTHEADVTYPEI,
OPERAND_RVKRNUM,
OPERAND_RVKRNUM_0_7,
OPERAND_RVKRNUM_1_10,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index bd899495812f44..07fe9a26ec4a6f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -216,6 +216,21 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
RISCVVType::printVType(Imm, O);
}
+void RISCVInstPrinter::printXTHeadVTypeI(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ unsigned Imm = MI->getOperand(OpNo).getImm();
+ unsigned VSEW = (Imm >> 2) & 0x7;
+ // Print the raw immediate for reserved values: vsew[2:0]=0b1xx,
+ // or non-zero in bits 7 and above.
+ if ((VSEW & 0x4) || (Imm >> 7) != 0) {
+ O << Imm;
+ return;
+ }
+ // Print the text form.
+ RISCVVType::printXTHeadVType(Imm, O);
+}
+
void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
index 4512bd5f4c4b7a..0da1a526a1bf42 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -48,6 +48,8 @@ class RISCVInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
+ void printXTHeadVTypeI(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O);
void printVMaskReg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printRlist(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 575bd4c9d3561d..6136059215023b 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -69,9 +69,16 @@ def RISCVAsmWriter : AsmWriter {
int PassSubtarget = 1;
}
+def RVV0p71AsmParserVariant : AsmParserVariant {
+ int Variant = 1;
+ string Name = "RVV0p71";
+}
+
def RISCV : Target {
let InstructionSet = RISCVInstrInfo;
let AssemblyParsers = [RISCVAsmParser];
+ let AssemblyParserVariants = [DefaultAsmParserVariant,
+ RVV0p71AsmParserVariant];
let AssemblyWriters = [RISCVAsmWriter];
let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 83619ccb24baa3..9b2748cf0748de 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1232,6 +1232,39 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+//===----------------------------------------------------------------------===//
+// T-Head in RuyiSDK specific features and extensions (mostly rvv 0.7.1)
+//===----------------------------------------------------------------------===//
+
+def FeatureVendorXTHeadV
+ : SubtargetFeature<"xtheadv", "HasVendorXTHeadV", "true",
+ "'xtheadv' (T-Head Base Vector Instructions)">;
+def HasVendorXTHeadV : Predicate<"Subtarget->hasVendorXTHeadV()">,
+ AssemblerPredicate<(all_of FeatureVendorXTHeadV),
+ "'xtheadv' (T-Head Base Vector Instructions)">;
+
+def FeatureVendorXTHeadVlsseg
+ : SubtargetFeature<"xtheadvlsseg", "HasVendorXTHeadVlsseg", "true",
+ "'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions)">;
+def HasVendorXTHeadVlsseg : Predicate<"Subtarget->hasVendorXTHeadVlsseg()">,
+ AssemblerPredicate<(all_of FeatureVendorXTHeadVlsseg),
+ "'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions)">;
+
+def FeatureVendorXTHeadVamo
+ : SubtargetFeature<"xtheadvamo", "HasVendorXTHeadVamo", "true",
+ "'xtheadvamo' (T-Head Vector AMO Operations)",
+ [FeatureStdExtA]>;
+def HasVendorXTHeadVamo : Predicate<"Subtarget->hasVendorXTHeadVamo()">,
+ AssemblerPredicate<(all_of FeatureVendorXTHeadVamo),
+ "'xtheadvamo' (T-Head Vector AMO Operations)">;
+
+def FeatureVendorXTHeadVediv
+ : SubtargetFeature<"xtheadvediv", "HasVendorXTHeadVediv", "true",
+ "'xtheadvediv' (T-Head Divided Element Extension)">;
+def HasVendorXTHeadVediv : Predicate<"Subtarget->hasVendorXTHeadVediv()">,
+ AssemblerPredicate<(all_of FeatureVendorXTHeadVediv),
+ "'xtheadvediv' (T-Head Divided Element Extension)">;
+
def FeatureForcedSWShadowStack : SubtargetFeature<
"forced-sw-shadow-stack", "HasForcedSWShadowStack", "true",
"Implement shadow stack with software.">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ef0d7cbc835d0d..1971b3ce3e7eef 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2019,6 +2019,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isUInt<10>(Imm);
break;
case RISCVOp::OPERAND_VTYPEI11:
+ case RISCVOp::OPERAND_XTHEADVTYPEI:
Ok = isUInt<11>(Imm);
break;
case RISCVOp::OPERAND_SIMM12:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e753c1f1add0c6..3d6375e15c8bf0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1996,6 +1996,7 @@ include "RISCVInstrInfoZicfiss.td"
include "RISCVInstrInfoXVentana.td"
include "RISCVInstrInfoXTHead.td"
+include "RISCVInstrInfoXTHeadV.td"
include "RISCVInstrInfoXSf.td"
include "RISCVInstrInfoSFB.td"
include "RISCVInstrInfoXCV.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
new file mode 100644
index 00000000000000..f8e531fd4c598d
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
@@ -0,0 +1,750 @@
+//===-- RISCVInstrInfoXTHeadV.td ---------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the standard 'V' Vector
+/// extension, version 0.7.1.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def XTHeadVTypeIAsmOperand : AsmOperandClass {
+ let Name = "XTHeadVTypeI";
+ let ParserMethod = "parseXTHeadVTypeI";
+ let DiagnosticType = "InvalidXTHeadVTypeI";
+ let RenderMethod = "addVTypeIOperands";
+}
+
+def XTHeadVTypeI : Operand<XLenVT> {
+ let ParserMatchClass = XTHeadVTypeIAsmOperand;
+ let PrintMethod = "printXTHeadVTypeI";
+ let DecoderMethod = "decodeUImmOperand<11>";
+ let OperandType = "OPERAND_XTHEADVTYPEI";
+ let OperandNamespace = "RISCVOp";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isUInt<11>(Imm);
+ return MCOp.isBareSymbolRef();
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+class XVLoadStore<bits<3> nf, RISCVOpcode opcode,
+ bits<3> mop, bits<3> width, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> rd;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop;
+ let Inst{25} = vm;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0, RVVConstraint = VMConstraint in {
+ class XVLxU<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b00000;
+ }
+ class XVLx<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b00000;
+ }
+ class XVLxUFF<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b10000;
+ }
+ class XVLxFF<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b10000;
+ }
+ class XVLSxU<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b010, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class XVLSx<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b110, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class XVLXxU<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b011, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class XVLXx<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_LOAD_FP, 0b111, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ class XVSx<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_STORE_FP, 0b000, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b00000;
+ }
+ class XVSSx<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_STORE_FP, 0b010, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class XVSXx<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_STORE_FP, 0b011, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class XVSUXx<bits<3> nf, bits<3> width, string opcodestr>
+ : XVLoadStore<nf, OPC_STORE_FP, 0b111, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+}
+
+multiclass VWSMAC_V_X<string opcodestr, bits<6> funct6> {
+ def V : VALUrVV<funct6, OPIVV, opcodestr # ".vv">,
+ Sched<[WriteVIWMulAddV_WorstCase, ReadVIWMulAddV_WorstCase,
+ ReadVIWMulAddV_WorstCase, ReadVMask]>;
+ def X : VALUrVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVIWMulAddX_WorstCase, ReadVIWMulAddV_WorstCase,
+ ReadVIWMulAddX_WorstCase, ReadVMask]>;
+}
+
+multiclass VWSMAC_X<string opcodestr, bits<6> funct6> {
+ def X : VALUrVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVIWMulAddX_WorstCase, ReadVIWMulAddV_WorstCase,
+ ReadVIWMulAddX_WorstCase, ReadVMask]>;
+}
+
+multiclass XVNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
+ def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
+ Sched<[WriteVNClipV_WorstCase, ReadVNClipV_WorstCase,
+ ReadVNClipV_WorstCase, ReadVMask]>;
+ def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVNClipX_WorstCase, ReadVNClipV_WorstCase,
+ ReadVNClipX_WorstCase, ReadVMask]>;
+ def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
+ Sched<[WriteVNClipI_WorstCase, ReadVNClipV_WorstCase,
+ ReadVMask]>;
+}
+
+multiclass XVNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
+ def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
+ Sched<[WriteVNShiftV_WorstCase, ReadVNShiftV_WorstCase,
+ ReadVNShiftV_WorstCase, ReadVMask]>;
+ def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVNShiftX_WorstCase, ReadVNShiftV_WorstCase,
+ ReadVNShiftX_WorstCase, ReadVMask]>;
+ def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
+ Sched<[WriteVNShiftI_WorstCase, ReadVNShiftV_WorstCase,
+ ReadVMask]>;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let AsmVariantName = "RVV0p71", DecoderNamespace = "RVV0p71" in {
+let Predicates = [HasVendorXTHeadV] in {
+// Configuration-Setting Instructions
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+def XVSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, XTHeadVTypeI:$vtypei),
+ "vsetvli", "$rd, $rs1, $vtypei">,
+ Sched<[WriteVSETVLI, ReadVSETVLI]>;
+def XVSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+ "vsetvl", "$rd, $rs1, $rs2">,
+ Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>;
+} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
+
+// Vector Unit-Stride Instructions
+def XVLB_V : XVLx<0b000, 0b000, "vlb.v">;
+def XVLH_V : XVLx<0b000, 0b101, "vlh.v">;
+def XVLW_V : XVLx<0b000, 0b110, "vlw.v">;
+def XVLBU_V : XVLxU<0b000, 0b000, "vlbu.v">;
+def XVLHU_V : XVLxU<0b000, 0b101, "vlhu.v">;
+def XVLWU_V : XVLxU<0b000, 0b110, "vlwu.v">;
+def XVLE_V : XVLxU<0b000, 0b111, "vle.v">;
+def XVSB_V : XVSx<0b000, 0b000, "vsb.v">;
+def XVSH_V : XVSx<0b000, 0b101, "vsh.v">;
+def XVSW_V : XVSx<0b000, 0b110, "vsw.v">;
+def XVSE_V : XVSx<0b000, 0b111, "vse.v">;
+
+// Vector Strided Instructions
+def XVLSB_V : XVLSx<0b000, 0b000, "vlsb.v">;
+def XVLSH_V : XVLSx<0b000, 0b101, "vlsh.v">;
+def XVLSW_V : XVLSx<0b000, 0b110, "vlsw.v">;
+def XVLSBU_V : XVLSxU<0b000, 0b000, "vlsbu.v">;
+def XVLSHU_V : XVLSxU<0b000, 0b101, "vlshu.v">;
+def XVLSWU_V : XVLSxU<0b000, 0b110, "vlswu.v">;
+def XVLSE_V : XVLSxU<0b000, 0b111, "vlse.v">;
+def XVSSB_V : XVSSx<0b000, 0b000, "vssb.v">;
+def XVSSH_V : XVSSx<0b000, 0b101, "vssh.v">;
+def XVSSW_V : XVSSx<0b000, 0b110, "vssw.v">;
+def XVSSE_V : XVSSx<0b000, 0b111, "vsse.v">;
+
+// Vector indexed loads and stores
+def XVLXB_V : XVLXx<0b000, 0b000, "vlxb.v">;
+def XVLXH_V : XVLXx<0b000, 0b101, "vlxh.v">;
+def XVLXW_V : XVLXx<0b000, 0b110, "vlxw.v">;
+def XVLXBU_V : XVLXxU<0b000, 0b000, "vlxbu.v">;
+def XVLXHU_V : XVLXxU<0b000, 0b101, "vlxhu.v">;
+def XVLXWU_V : XVLXxU<0b000, 0b110, "vlxwu.v">;
+def XVLXE_V : XVLXxU<0b000, 0b111, "vlxe.v">;
+def XVSXB_V : XVSXx<0b000, 0b000, "vsxb.v">;
+def XVSXH_V : XVSXx<0b000, 0b101, "vsxh.v">;
+def XVSXW_V : XVSXx<0b000, 0b110, "vsxw.v">;
+def XVSXE_V : XVSXx<0b000, 0b111, "vsxe.v">;
+def XVSUXB_V : XVSUXx<0b000, 0b000, "vsuxb.v">;
+def XVSUXH_V : XVSUXx<0b000, 0b101, "vsuxh.v">;
+def XVSUXW_V : XVSUXx<0b000, 0b110, "vsuxw.v">;
+def XVSUXE_V : XVSUXx<0b000, 0b111, "vsuxe.v">;
+
+// Unit-stride Fault-Only-First Loads
+def XVLBFF_V : XVLxFF<0b000, 0b000, "vlbff.v">;
+def XVLHFF_V : XVLxFF<0b000, 0b101, "vlhff.v">;
+def XVLWFF_V : XVLxFF<0b000, 0b110, "vlwff.v">;
+def XVLBUFF_V : XVLxUFF<0b000, 0b000, "vlbuff.v">;
+def XVLHUFF_V : XVLxUFF<0b000, 0b101, "vlhuff.v">;
+def XVLWUFF_V : XVLxUFF<0b000, 0b110, "vlwuff.v">;
+def XVLEFF_V : XVLxUFF<0b000, 0b111, "vleff.v">;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg] in {
+foreach nf=2-8 in {
+ // Vector Unit-Stride Segment Loads and Stores
+ def XVLSEG#nf#B_V : XVLx<!add(nf, -1), 0b000, "vlseg"#nf#"b.v">;
+ def XVLSEG#nf#H_V : XVLx<!add(nf, -1), 0b101, "vlseg"#nf#"h.v">;
+ def XVLSEG#nf#W_V : XVLx<!add(nf, -1), 0b110, "vlseg"#nf#"w.v">;
+ def XVLSEG#nf#BU_V : XVLxU<!add(nf, -1), 0b000, "vlseg"#nf#"bu.v">;
+ def XVLSEG#nf#HU_V : XVLxU<!add(nf, -1), 0b101, "vlseg"#nf#"hu.v">;
+ def XVLSEG#nf#WU_V : XVLxU<!add(nf, -1), 0b110, "vlseg"#nf#"wu.v">;
+ def XVLSEG#nf#E_V : XVLxU<!add(nf, -1), 0b111, "vlseg"#nf#"e.v">;
+ def XVSSEG#nf#B_V : XVSx<!add(nf, -1), 0b000, "vsseg"#nf#"b.v">;
+ def XVSSEG#nf#H_V : XVSx<!add(nf, -1), 0b101, "vsseg"#nf#"h.v">;
+ def XVSSEG#nf#W_V : XVSx<!add(nf, -1), 0b110, "vsseg"#nf#"w.v">;
+ def XVSSEG#nf#E_V : XVSx<!add(nf, -1), 0b111, "vsseg"#nf#"e.v">;
+ def XVLSEG#nf#BFF_V : XVLxFF<!add(nf, -1), 0b000, "vlseg"#nf#"bff.v">;
+ def XVLSEG#nf#HFF_V : XVLxFF<!add(nf, -1), 0b101, "vlseg"#nf#"hff.v">;
+ def XVLSEG#nf#WFF_V : XVLxFF<!add(nf, -1), 0b110, "vlseg"#nf#"wff.v">;
+ def XVLSEG#nf#BUFF_V : XVLxUFF<!add(nf, -1), 0b000, "vlseg"#nf#"buff.v">;
+ def XVLSEG#nf#HUFF_V : XVLxUFF<!add(nf, -1), 0b101, "vlseg"#nf#"huff.v">;
+ def XVLSEG#nf#WUFF_V : XVLxUFF<!add(nf, -1), 0b110, "vlseg"#nf#"wuff.v">;
+ def XVLSEG#nf#EFF_V : XVLxUFF<!add(nf, -1), 0b111, "vlseg"#nf#"eff.v">;
+
+ // Vector Strided Segment Loads and Stores
+ def XVLSSEG#nf#B_V : XVLSx<!add(nf, -1), 0b000, "vlsseg"#nf#"b.v">;
+ def XVLSSEG#nf#H_V : XVLSx<!add(nf, -1), 0b101, "vlsseg"#nf#"h.v">;
+ def XVLSSEG#nf#W_V : XVLSx<!add(nf, -1), 0b110, "vlsseg"#nf#"w.v">;
+ def XVLSSEG#nf#BU_V : XVLSxU<!add(nf, -1), 0b000, "vlsseg"#nf#"bu.v">;
+ def XVLSSEG#nf#HU_V : XVLSxU<!add(nf, -1), 0b101, "vlsseg"#nf#"hu.v">;
+ def XVLSSEG#nf#WU_V : XVLSxU<!add(nf, -1), 0b110, "vlsseg"#nf#"wu.v">;
+ def XVLSSEG#nf#E_V : XVLSxU<!add(nf, -1), 0b111, "vlsseg"#nf#"e.v">;
+ def XVSSSEG#nf#B_V : XVSSx<!add(nf, -1), 0b000, "vssseg"#nf#"b.v">;
+ def XVSSSEG#nf#H_V : XVSSx<!add(nf, -1), 0b101, "vssseg"#nf#"h.v">;
+ def XVSSSEG#nf#W_V : XVSSx<!add(nf, -1), 0b110, "vssseg"#nf#"w.v">;
+ def XVSSSEG#nf#E_V : XVSSx<!add(nf, -1), 0b111, "vssseg"#nf#"e.v">;
+
+ // Vector Indexed Segment Loads and Stores
+ def XVLXSEG#nf#B_V : XVLXx<!add(nf, -1), 0b000, "vlxseg"#nf#"b.v">;
+ def XVLXSEG#nf#H_V : XVLXx<!add(nf, -1), 0b101, "vlxseg"#nf#"h.v">;
+ def XVLXSEG#nf#W_V : XVLXx<!add(nf, -1), 0b110, "vlxseg"#nf#"w.v">;
+ def XVLXSEG#nf#BU_V : XVLXxU<!add(nf, -1), 0b000, "vlxseg"#nf#"bu.v">;
+ def XVLXSEG#nf#HU_V : XVLXxU<!add(nf, -1), 0b101, "vlxseg"#nf#"hu.v">;
+ def XVLXSEG#nf#WU_V : XVLXxU<!add(nf, -1), 0b110, "vlxseg"#nf#"wu.v">;
+ def XVLXSEG#nf#E_V : XVLXxU<!add(nf, -1), 0b111, "vlxseg"#nf#"e.v">;
+ def XVSXSEG#nf#B_V : XVSXx<!add(nf, -1), 0b000, "vsxseg"#nf#"b.v">;
+ def XVSXSEG#nf#H_V : XVSXx<!add(nf, -1), 0b101, "vsxseg"#nf#"h.v">;
+ def XVSXSEG#nf#W_V : XVSXx<!add(nf, -1), 0b110, "vsxseg"#nf#"w.v">;
+ def XVSXSEG#nf#E_V : XVSXx<!add(nf, -1), 0b111, "vsxseg"#nf#"e.v">;
+}
+} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg]
+
+let Predicates = [HasVendorXTHeadV] in {
+// Vector Single-Width Integer Add and Subtract
+defm XVADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
+defm XVSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
+defm XVRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
+
+// Vector Widening Integer Add/Subtract
+// Refer to 11.2 Widening Vector Arithmetic Instructions
+// The destination vector register group cannot overlap a source vector
+// register group of a different element width (including the mask register
+// if masked), otherwise an illegal instruction exception is raised.
+let Constraints = "@earlyclobber $vd" in {
+let RVVConstraint = WidenV in {
+defm XVWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000, "v">;
+defm XVWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010, "v">;
+defm XVWADD_V : VALU_MV_V_X<"vwadd", 0b110001, "v">;
+defm XVWSUB_V : VALU_MV_V_X<"vwsub", 0b110011, "v">;
+} // RVVConstraint = WidenV
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+let RVVConstraint = WidenW in {
+defm XVWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">;
+defm XVWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">;
+defm XVWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">;
+defm XVWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
+} // RVVConstraint = WidenW
+} // Constraints = "@earlyclobber $vd"
+
+// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+defm XVADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
+defm XVMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
+defm XVMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
+defm XVSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
+defm XVMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
+defm XVMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
+
+// Vector Bitwise Logical Instructions
+defm XVAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
+defm XVOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
+defm XVXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
+
+// Vector Single-Width Bit Shift Instructions
+defm XVSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101>;
+defm XVSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000>;
+defm XVSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001>;
+
+// Vector Narrowing Integer Right Shift Instructions
+// Refer to 11.3. Narrowing Vector Arithmetic Instructions
+// The destination vector register group cannot overlap the first source
+// vector register group (specified by vs2). The destination vector register
+// group cannot overlap the mask register if used, unless LMUL=1.
+let Constraints = "@earlyclobber $vd" in {
+defm XVNSRL_W : XVNSHT_IV_V_X_I<"vnsrl", 0b101100>;
+defm XVNSRA_W : XVNSHT_IV_V_X_I<"vnsra", 0b101101>;
+} // Constraints = "@earlyclobber $vd"
+
+// Vector Integer Comparison Instructions
+let RVVConstraint = NoConstraint in {
+defm XVMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>;
+defm XVMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>;
+defm XVMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>;
+defm XVMSLT_V : VCMP_IV_V_X<"vmslt", 0b011011>;
+defm XVMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>;
+defm XVMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>;
+defm XVMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>;
+defm XVMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>;
+} // RVVConstraint = NoConstraint
+
+// Vector Integer Min/Max Instructions
+defm XVMINU_V : VCMP_IV_V_X<"vminu", 0b000100>;
+defm XVMIN_V : VCMP_IV_V_X<"vmin", 0b000101>;
+defm XVMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>;
+defm XVMAX_V : VCMP_IV_V_X<"vmax", 0b000111>;
+
+// Vector Single-Width Integer Multiply Instructions
+defm XVMUL_V : VMUL_MV_V_X<"vmul", 0b100101>;
+defm XVMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>;
+defm XVMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>;
+defm XVMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>;
+
+// Vector Integer Divide Instructions
+defm XVDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>;
+defm XVDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>;
+defm XVREMU_V : VDIV_MV_V_X<"vremu", 0b100010>;
+defm XVREM_V : VDIV_MV_V_X<"vrem", 0b100011>;
+
+// Vector Widening Integer Multiply Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm XVWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>;
+defm XVWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>;
+defm XVWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+
+// Vector Single-Width Integer Multiply-Add Instructions
+defm XVMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>;
+defm XVNMSAC_V : VMAC_MV_V_X<"vnmsac", 0b101111>;
+defm XVMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>;
+defm XVNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>;
+
+// Vector Widening Integer Multiply-Add Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm XVWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>;
+defm XVWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>;
+defm XVWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>;
+defm XVWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+
+// Vector Integer Merge Instructions
+defm XVMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>;
+
+// Vector Integer Move Instructions
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1,
+ RVVConstraint = NoConstraint in {
+// op vd, vs1
+def XVMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd),
+ (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">,
+ Sched<[WriteVIMovV_WorstCase, ReadVIMovV_WorstCase]>;
+// op vd, rs1
+def XVMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd),
+ (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">,
+ Sched<[WriteVIMovX_WorstCase, ReadVIMovX_WorstCase]>;
+// op vd, imm
+def XVMV_V_I : RVInstIVI<0b010111, (outs VR:$vd),
+ (ins simm5:$imm), "vmv.v.i", "$vd, $imm">,
+ Sched<[WriteVIMovI_WorstCase]>;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+// Vector Fixed-Point Arithmetic Instructions
+defm XVSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>;
+defm XVSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>;
+defm XVSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>;
+defm XVSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>;
+
+// Vector Single-Width Averaging Add and Subtract
+defm XVAADD_V : VSALU_IV_V_X_I<"vaadd", 0b100100>;
+defm XVASUB_V : VSALU_IV_V_X<"vasub", 0b100110>;
+
+// Vector Single-Width Fractional Multiply with Rounding and Saturation
+defm XVSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>;
+
+// Vector Widening Saturating Scaled Multiply-Add
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm XVWSMACCU_V : VWSMAC_V_X<"vwsmaccu", 0b111100>;
+defm XVWSMACC_V : VWSMAC_V_X<"vwsmacc", 0b111101>;
+defm XVWSMACCSU_V : VWSMAC_V_X<"vwsmaccsu", 0b111110>;
+defm XVWSMACCUS_V : VWSMAC_X<"vwsmaccus", 0b111111>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+
+// Vector Single-Width Scaling Shift Instructions
+defm XVSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010>;
+defm XVSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011>;
+
+// Vector Narrowing Fixed-Point Clip Instructions
+let Constraints = "@earlyclobber $vd" in {
+defm XVNCLIPU_W : XVNCLP_IV_V_X_I<"vnclipu", 0b101110>;
+defm XVNCLIP_W : XVNCLP_IV_V_X_I<"vnclip", 0b101111>;
+} // Constraints = "@earlyclobber $vd"
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
+// Vector Single-Width Floating-Point Add/Subtract Instructions
+let Uses = [FRM], mayRaiseFPException = true in {
+defm XVFADD_V : VALU_FV_V_F<"vfadd", 0b000000>;
+defm XVFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>;
+defm XVFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>;
+}
+
+// Vector Widening Floating-Point Add/Subtract Instructions
+let Constraints = "@earlyclobber $vd",
+ Uses = [FRM],
+ mayRaiseFPException = true in {
+let RVVConstraint = WidenV in {
+defm XVFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000, "v">;
+defm XVFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010, "v">;
+} // RVVConstraint = WidenV
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+let RVVConstraint = WidenW in {
+defm XVFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">;
+defm XVFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">;
+} // RVVConstraint = WidenW
+} // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true
+
+// Vector Single-Width Floating-Point Multiply/Divide Instructions
+let Uses = [FRM], mayRaiseFPException = true in {
+defm XVFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>;
+defm XVFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>;
+defm XVFRDIV_V : VDIV_FV_F<"vfrdiv", 0b100001>;
+}
+
+// Vector Widening Floating-Point Multiply
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
+ Uses = [FRM], mayRaiseFPException = true in {
+defm XVFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
+
+// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+let Uses = [FRM], mayRaiseFPException = true in {
+defm XVFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>;
+defm XVFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>;
+defm XVFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>;
+defm XVFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>;
+defm XVFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>;
+defm XVFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>;
+defm XVFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>;
+defm XVFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>;
+}
+
+// Vector Widening Floating-Point Fused Multiply-Add Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
+ Uses = [FRM], mayRaiseFPException = true in {
+defm XVFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>;
+defm XVFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>;
+defm XVFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>;
+defm XVFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
+
+// Vector Floating-Point Square-Root Instruction
+let Uses = [FRM], mayRaiseFPException = true in {
+defm XVFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
+}
+
+// Vector Floating-Point MIN/MAX Instructions
+let mayRaiseFPException = true in {
+defm XVFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>;
+defm XVFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>;
+}
+
+// Vector Floating-Point Sign-Injection Instructions
+defm XVFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>;
+defm XVFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>;
+defm XVFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>;
+
+// Vector Floating-Point Compare Instructions
+let RVVConstraint = NoConstraint, mayRaiseFPException = true in {
+defm XVMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>;
+defm XVMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>;
+defm XVMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>;
+defm XVMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>;
+defm XVMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>;
+defm XVMFGE_V : VCMP_FV_F<"vmfge", 0b011111>;
+defm XVMFORD_V : VCMP_FV_V_F<"vmford", 0b011010>;
+} // RVVConstraint = NoConstraint, mayRaiseFPException = true
+
+// Vector Floating-Point Classify Instruction
+defm XVFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+
+// Vector Floating-Point Merge Instruction
+let vm = 0 in
+def XVFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
+ (ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
+ "vfmerge.vfm", "$vd, $vs2, $rs1, v0">,
+ Sched<[WriteVFMergeV_WorstCase, ReadVFMergeV_WorstCase,
+ ReadVFMergeF_WorstCase, ReadVMask]>;
+
+// Vector Floating-Point Move Instruction
+let RVVConstraint = NoConstraint in
+let vm = 1, vs2 = 0 in
+def XVFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
+ (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">,
+ Sched<[WriteVFMovV_WorstCase, ReadVFMovF_WorstCase]>;
+
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+// Single-Width Floating-Point/Integer Type-Convert Instructions
+let mayRaiseFPException = true in {
+let Uses = [FRM] in {
+defm XVFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
+defm XVFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
+defm XVFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
+defm XVFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
+}
+} // mayRaiseFPException = true
+
+// Widening Floating-Point/Integer Type-Convert Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt,
+ mayRaiseFPException = true in {
+let Uses = [FRM] in {
+defm XVFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
+defm XVFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
+}
+defm XVFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
+defm XVFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
+defm XVFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
+
+// Narrowing Floating-Point/Integer Type-Convert Instructions
+let Constraints = "@earlyclobber $vd", mayRaiseFPException = true in {
+let Uses = [FRM] in {
+defm XVFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.v", 0b100010, 0b10000>;
+defm XVFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.v", 0b100010, 0b10001>;
+defm XVFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.v", 0b100010, 0b10010>;
+defm XVFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.v", 0b100010, 0b10011>;
+defm XVFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.v", 0b100010, 0b10100>;
+}
+} // Constraints = "@earlyclobber $vd", mayRaiseFPException = true
+} // Predicates = [HasVendorXTHeadV, HasStdExtF]
+
+let Predicates = [HasVendorXTHeadV] in {
+// Vector Single-Width Integer Reduction Instructions
+let RVVConstraint = NoConstraint in {
+defm XVREDSUM : VRED_MV_V<"vredsum", 0b000000>;
+defm XVREDMAXU : VRED_MV_V<"vredmaxu", 0b000110>;
+defm XVREDMAX : VRED_MV_V<"vredmax", 0b000111>;
+defm XVREDMINU : VRED_MV_V<"vredminu", 0b000100>;
+defm XVREDMIN : VRED_MV_V<"vredmin", 0b000101>;
+defm XVREDAND : VRED_MV_V<"vredand", 0b000001>;
+defm XVREDOR : VRED_MV_V<"vredor", 0b000010>;
+defm XVREDXOR : VRED_MV_V<"vredxor", 0b000011>;
+} // RVVConstraint = NoConstraint
+
+// Vector Widening Integer Reduction Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+defm XVWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>;
+defm XVWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
+
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
+// Vector Single-Width Floating-Point Reduction Instructions
+let RVVConstraint = NoConstraint in {
+let Uses = [FRM], mayRaiseFPException = true in {
+defm XVFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>;
+defm XVFREDUSUM : VRED_FV_V<"vfredsum", 0b000001>;
+}
+let mayRaiseFPException = true in {
+defm XVFREDMAX : VRED_FV_V<"vfredmax", 0b000111>;
+defm XVFREDMIN : VRED_FV_V<"vfredmin", 0b000101>;
+}
+} // RVVConstraint = NoConstraint
+
+// Vector Widening Floating-Point Reduction Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+let Uses = [FRM], mayRaiseFPException = true in {
+defm XVFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>;
+defm XVFWREDUSUM : VWRED_FV_V<"vfwredsum", 0b110001>;
+}
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
+} // Predicates = [HasVendorXTHeadV, HasStdExtF]
+
+let Predicates = [HasVendorXTHeadV] in {
+// Vector Mask-Register Logical Instructions
+let RVVConstraint = NoConstraint in {
+defm XVMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">;
+defm XVMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">;
+defm XVMANDN_M : VMALU_MV_Mask<"vmandnot", 0b011000, "m">;
+defm XVMXOR_M : VMALU_MV_Mask<"vmxor", 0b011011, "m">;
+defm XVMOR_M : VMALU_MV_Mask<"vmor", 0b011010, "m">;
+defm XVMNOR_M : VMALU_MV_Mask<"vmnor", 0b011110, "m">;
+defm XVMORN_M : VMALU_MV_Mask<"vmornot", 0b011100, "m">;
+defm XVMXNOR_M : VMALU_MV_Mask<"vmxnor", 0b011111, "m">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+ RVVConstraint = NoConstraint in {
+
+// Vector mask population count vmpopc
+def XVMPOPC_M : RVInstV<0b010100, 0b00000, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, VMaskOp:$vm),
+ "vmpopc.m", "$vd, $vs2$vm">,
+ Sched<[WriteVMPopV_WorstCase, ReadVMPopV_WorstCase,
+ ReadVMask]>;
+
+// vmfirst find-first-set mask bit
+def XVMFIRST_M : RVInstV<0b010101, 0b00000, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, VMaskOp:$vm),
+ "vmfirst.m", "$vd, $vs2$vm">,
+ Sched<[WriteVMFFSV_WorstCase, ReadVMFFSV_WorstCase,
+ ReadVMask]>;
+
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
+
+// vmsbf.m set-before-first mask bit
+defm XVMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010110, 0b00001>;
+// vmsif.m set-including-first mask bit
+defm XVMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010110, 0b00011>;
+// vmsof.m set-only-first mask bit
+defm XVMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010110, 0b00010>;
+// Vector Iota Instruction
+ defm XVIOTA_M : VMIOT_MV_V<"viota.m", 0b010110, 0b10000>;
+
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// Vector Element Index Instruction
+let vs2 = 0 in
+def XVID_V : RVInstV<0b010110, 0b10001, OPMVV, (outs VR:$vd),
+ (ins VMaskOp:$vm), "vid.v", "$vd$vm">,
+ Sched<[WriteVMIdxV_WorstCase, ReadVMask]>;
+
+let vm = 1, RVVConstraint = NoConstraint in {
+// Integer Extract Instruction
+def XVEXT_X_V : RVInstVX<0b001100, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, GPR:$rs1),
+ "vext.x.v", "$vd, $vs2, $rs1">,
+ Sched<[WriteVIMovVX, ReadVIMovVX,
+ ReadVIMovXX]>;
+
+// Integer Scalar Move Instruction
+let Constraints = "$vd = $vd_wb" in
+def XVMV_S_X : RVInstV2<0b001101, 0b00000, OPMVX, (outs VR:$vd_wb),
+ (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
+ Sched<[WriteVIMovXV, ReadVIMovXV,
+ ReadVIMovXX]>;
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
+ RVVConstraint = NoConstraint in {
+// Floating-Point Scalar Move Instructions
+def XVFMV_F_S : RVInstV<0b001100, 0b00000, OPFVV, (outs FPR32:$vd),
+ (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
+ Sched<[WriteVFMovVF, ReadVFMovVF]>;
+let Constraints = "$vd = $vd_wb" in
+def XVFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb),
+ (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
+ Sched<[WriteVFMovFV, ReadVFMovFV,
+ ReadVFMovFX]>;
+
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
+} // Predicates = [HasVendorXTHeadV, HasStdExtF]
+
+let Predicates = [HasVendorXTHeadV] in {
+// Vector Slide Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
+defm XVSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110>;
+defm XVSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+defm XVSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111>;
+defm XVSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
+
+// Vector Register Gather Instruction
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
+defm XVRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
+
+// Vector Compress Instruction
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
+defm XVCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
+} // Predicates = [HasVendorXTHeadV]
+} // AsmVariantName = "RVV0p71", DecoderNamespace = "RVV0p71"
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 0d95e3a9b81962..1a10b572bebdbe 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -145,6 +145,24 @@ unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
return VTypeI;
}
+// Encode VTYPE into the binary format used by the the VSETVLI instruction in
+// XTHeadVector extension.
+//
+// Bits | Name | Description
+// -----+------------+------------------------------------------------
+// 6:5 | vediv[1:0] | Used by EDIV extension
+// 4:2 | vsew[2:0] | Standard element width (SEW) setting
+// 1:0 | vlmul[1:0] | Vector register group multiplier (LMUL) setting
+unsigned encodeXTHeadVTYPE(unsigned SEW, unsigned LMUL,
+ unsigned EDIV) {
+ unsigned VSEWBits = encodeSEW(SEW);
+ unsigned VLMULBits = encodeLMUL(LMUL, false);
+ unsigned VEDIVBits = encodeEDIV(EDIV);
+ unsigned VTypeI = (VEDIVBits << 5) | (VSEWBits << 2) | (VLMULBits & 0x3);
+
+ return VTypeI;
+}
+
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL) {
switch (VLMUL) {
default:
@@ -186,6 +204,16 @@ void printVType(unsigned VType, raw_ostream &OS) {
OS << ", mu";
}
+void printXTHeadVType(unsigned VType, raw_ostream &OS) {
+ unsigned VEDIV = (VType >> 5) & 0x3;
+ unsigned VSEW = (VType >> 2) & 0x7;
+ unsigned VLMUL = VType & 0x3;
+
+ OS << "e" << RISCVVType::decodeVSEW(VSEW);
+ OS << ", m" << (1U << VLMUL);
+ OS << ", d" << (1U << VEDIV);
+}
+
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
unsigned LMul;
bool Fractional;
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 09daeee2c1b385..07ab9ee0a39ea8 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -428,3 +428,15 @@
.attribute arch, "rv64i_supm0p8"
# CHECK: attribute 5, "rv64i2p1_supm0p8"
+
+.attribute arch, "rv32i_xtheadvector"
+# CHECK: attribute 5, "rv32i2p1_xtheadvector1p0"
+
+.attribute arch, "rv32i_xtheadvector_xtheadzvamo"
+# CHECK: attribute 5, "rv32i2p1_a2p1_xtheadvector1p0_xtheadzvamo1p0"
+
+.attribute arch, "rv32i_xtheadvector"
+# CHECK: attribute 5, "rv32i2p1_xtheadvector1p0"
+
+.attribute arch, "rv64i_xtheadvector_xtheadzvamo"
+# CHECK: attribute 5, "rv64i2p1_a2p1_xtheadvector1p0_xtheadzvamo1p0"
diff --git a/llvm/test/MC/RISCV/xtheadvector/add.s b/llvm/test/MC/RISCV/xtheadvector/add.s
new file mode 100644
index 00000000000000..a1735229f64715
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/add.s
@@ -0,0 +1,306 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vadd.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 00 <unknown>
+
+th.vadd.vv v8, v4, v20
+# CHECK-INST: th.vadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 02 <unknown>
+
+th.vadd.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 00 <unknown>
+
+th.vadd.vx v8, v4, a0
+# CHECK-INST: th.vadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 02 <unknown>
+
+th.vadd.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vadd.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 00 <unknown>
+
+th.vadd.vi v8, v4, 15
+# CHECK-INST: th.vadd.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 02 <unknown>
+
+th.vwaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vwaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a c0 <unknown>
+
+th.vwaddu.vv v8, v4, v20
+# CHECK-INST: th.vwaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a c2 <unknown>
+
+th.vwaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vwaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 c0 <unknown>
+
+th.vwaddu.vx v8, v4, a0
+# CHECK-INST: th.vwaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 c2 <unknown>
+
+th.vwadd.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vwadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a c4 <unknown>
+
+th.vwadd.vv v8, v4, v20
+# CHECK-INST: th.vwadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a c6 <unknown>
+
+th.vwadd.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vwadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 c4 <unknown>
+
+th.vwadd.vx v8, v4, a0
+# CHECK-INST: th.vwadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 c6 <unknown>
+
+th.vwaddu.wv v8, v4, v20, v0.t
+# CHECK-INST: th.vwaddu.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a d0 <unknown>
+
+th.vwaddu.wv v8, v4, v20
+# CHECK-INST: th.vwaddu.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a d2 <unknown>
+
+th.vwaddu.wx v8, v4, a0, v0.t
+# CHECK-INST: th.vwaddu.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 d0 <unknown>
+
+th.vwaddu.wx v8, v4, a0
+# CHECK-INST: th.vwaddu.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 d2 <unknown>
+
+th.vwadd.wv v8, v4, v20, v0.t
+# CHECK-INST: th.vwadd.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a d4 <unknown>
+
+th.vwadd.wv v8, v4, v20
+# CHECK-INST: th.vwadd.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a d6 <unknown>
+
+th.vwadd.wx v8, v4, a0, v0.t
+# CHECK-INST: th.vwadd.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 d4 <unknown>
+
+th.vwadd.wx v8, v4, a0
+# CHECK-INST: th.vwadd.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 d6 <unknown>
+
+th.vadc.vvm v8, v4, v20, v0
+# CHECK-INST: th.vadc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 42 <unknown>
+
+th.vadc.vvm v4, v4, v20, v0
+# CHECK-INST: th.vadc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 02 4a 42 <unknown>
+
+th.vadc.vvm v8, v4, v8, v0
+# CHECK-INST: th.vadc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 44 42 <unknown>
+
+th.vadc.vxm v8, v4, a0, v0
+# CHECK-INST: th.vadc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 42 <unknown>
+
+th.vadc.vim v8, v4, 15, v0
+# CHECK-INST: th.vadc.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 42 <unknown>
+
+th.vmadc.vvm v8, v4, v20, v0
+# CHECK-INST: th.vmadc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x46]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 46 <unknown>
+
+th.vmadc.vvm v4, v4, v20, v0
+# CHECK-INST: th.vmadc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x46]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 02 4a 46 <unknown>
+
+th.vmadc.vvm v8, v4, v8, v0
+# CHECK-INST: th.vmadc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x46]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 44 46 <unknown>
+
+th.vmadc.vxm v8, v4, a0, v0
+# CHECK-INST: th.vmadc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 46 <unknown>
+
+th.vmadc.vim v8, v4, 15, v0
+# CHECK-INST: th.vmadc.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x46]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 46 <unknown>
+
+th.vsaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vsaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 80 <unknown>
+
+th.vsaddu.vv v8, v4, v20
+# CHECK-INST: th.vsaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 82 <unknown>
+
+th.vsaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vsaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 80 <unknown>
+
+th.vsaddu.vx v8, v4, a0
+# CHECK-INST: th.vsaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 82 <unknown>
+
+th.vsaddu.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vsaddu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 80 <unknown>
+
+th.vsaddu.vi v8, v4, 15
+# CHECK-INST: th.vsaddu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 82 <unknown>
+
+th.vsadd.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vsadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x84]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 84 <unknown>
+
+th.vsadd.vv v8, v4, v20
+# CHECK-INST: th.vsadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x86]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 86 <unknown>
+
+th.vsadd.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vsadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 84 <unknown>
+
+th.vsadd.vx v8, v4, a0
+# CHECK-INST: th.vsadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 86 <unknown>
+
+th.vsadd.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vsadd.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x84]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 84 <unknown>
+
+th.vsadd.vi v8, v4, 15
+# CHECK-INST: th.vsadd.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x86]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 86 <unknown>
+
+th.vaadd.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vaadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 90 <unknown>
+
+th.vaadd.vv v8, v4, v20
+# CHECK-INST: th.vaadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 92 <unknown>
+
+th.vaadd.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vaadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 90 <unknown>
+
+th.vaadd.vx v8, v4, a0
+# CHECK-INST: th.vaadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 92 <unknown>
+
+th.vaadd.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vaadd.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 90 <unknown>
+
+th.vaadd.vi v8, v4, 15
+# CHECK-INST: th.vaadd.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 92 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/and.s b/llvm/test/MC/RISCV/xtheadvector/and.s
new file mode 100644
index 00000000000000..6cff7f853ea985
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/and.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vand.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vand.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x24]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 24 <unknown>
+
+th.vand.vv v8, v4, v20
+# CHECK-INST: th.vand.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x26]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 26 <unknown>
+
+th.vand.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vand.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 24 <unknown>
+
+th.vand.vx v8, v4, a0
+# CHECK-INST: th.vand.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 26 <unknown>
+
+th.vand.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vand.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x24]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 24 <unknown>
+
+th.vand.vi v8, v4, 15
+# CHECK-INST: th.vand.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x26]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 26 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/clip.s b/llvm/test/MC/RISCV/xtheadvector/clip.s
new file mode 100644
index 00000000000000..30d90c89242b74
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/clip.s
@@ -0,0 +1,78 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vnclipu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vnclipu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a b8 <unknown>
+
+th.vnclipu.vv v8, v4, v20
+# CHECK-INST: th.vnclipu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xba]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a ba <unknown>
+
+th.vnclipu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vnclipu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 b8 <unknown>
+
+th.vnclipu.vx v8, v4, a0
+# CHECK-INST: th.vnclipu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xba]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 ba <unknown>
+
+th.vnclipu.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vnclipu.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f b8 <unknown>
+
+th.vnclipu.vi v8, v4, 31
+# CHECK-INST: th.vnclipu.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xba]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f ba <unknown>
+
+th.vnclip.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vnclip.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a bc <unknown>
+
+th.vnclip.vv v8, v4, v20
+# CHECK-INST: th.vnclip.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a be <unknown>
+
+th.vnclip.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vnclip.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 bc <unknown>
+
+th.vnclip.vx v8, v4, a0
+# CHECK-INST: th.vnclip.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 be <unknown>
+
+th.vnclip.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vnclip.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f bc <unknown>
+
+th.vnclip.vi v8, v4, 31
+# CHECK-INST: th.vnclip.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f be <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/compare.s b/llvm/test/MC/RISCV/xtheadvector/compare.s
new file mode 100644
index 00000000000000..527598c0b383e1
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/compare.s
@@ -0,0 +1,253 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmslt.vv v0, v4, v20, v0.t
+# CHECK-INST: th.vmslt.vv v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x00,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 00 4a 6c <unknown>
+
+th.vmseq.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmseq.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 60 <unknown>
+
+th.vmseq.vv v8, v4, v20
+# CHECK-INST: th.vmseq.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 62 <unknown>
+
+th.vmseq.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmseq.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 60 <unknown>
+
+th.vmseq.vx v8, v4, a0
+# CHECK-INST: th.vmseq.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 62 <unknown>
+
+th.vmseq.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vmseq.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 60 <unknown>
+
+th.vmseq.vi v8, v4, 15
+# CHECK-INST: th.vmseq.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 62 <unknown>
+
+th.vmsne.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmsne.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 64 <unknown>
+
+th.vmsne.vv v8, v4, v20
+# CHECK-INST: th.vmsne.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 66 <unknown>
+
+th.vmsne.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmsne.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 64 <unknown>
+
+th.vmsne.vx v8, v4, a0
+# CHECK-INST: th.vmsne.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 66 <unknown>
+
+th.vmsne.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vmsne.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x64]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 64 <unknown>
+
+th.vmsne.vi v8, v4, 15
+# CHECK-INST: th.vmsne.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x66]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 66 <unknown>
+
+th.vmsltu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmsltu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 68 <unknown>
+
+th.vmsltu.vv v8, v4, v20
+# CHECK-INST: th.vmsltu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 6a <unknown>
+
+th.vmsltu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmsltu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 68 <unknown>
+
+th.vmsltu.vx v8, v4, a0
+# CHECK-INST: th.vmsltu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 6a <unknown>
+
+th.vmslt.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmslt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 6c <unknown>
+
+th.vmslt.vv v8, v4, v20
+# CHECK-INST: th.vmslt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 6e <unknown>
+
+th.vmslt.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmslt.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 6c <unknown>
+
+th.vmslt.vx v8, v4, a0
+# CHECK-INST: th.vmslt.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 6e <unknown>
+
+th.vmsleu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmsleu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 70 <unknown>
+
+th.vmsleu.vv v8, v4, v20
+# CHECK-INST: th.vmsleu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 72 <unknown>
+
+th.vmsleu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmsleu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x70]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 70 <unknown>
+
+th.vmsleu.vx v8, v4, a0
+# CHECK-INST: th.vmsleu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x72]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 72 <unknown>
+
+th.vmsleu.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vmsleu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x70]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 70 <unknown>
+
+th.vmsleu.vi v8, v4, 15
+# CHECK-INST: th.vmsleu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x72]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 72 <unknown>
+
+th.vmsle.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmsle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x74]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 74 <unknown>
+
+th.vmsle.vv v8, v4, v20
+# CHECK-INST: th.vmsle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x76]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 76 <unknown>
+
+th.vmsle.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmsle.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x74]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 74 <unknown>
+
+th.vmsle.vx v8, v4, a0
+# CHECK-INST: th.vmsle.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x76]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 76 <unknown>
+
+th.vmsle.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vmsle.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x74]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 74 <unknown>
+
+th.vmsle.vi v8, v4, 15
+# CHECK-INST: th.vmsle.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x76]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 76 <unknown>
+
+th.vmsgtu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmsgtu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x78]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 78 <unknown>
+
+th.vmsgtu.vx v8, v4, a0
+# CHECK-INST: th.vmsgtu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 7a <unknown>
+
+th.vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x78]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 78 <unknown>
+
+th.vmsgtu.vi v8, v4, 15
+# CHECK-INST: th.vmsgtu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 7a <unknown>
+
+th.vmsgt.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmsgt.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 7c <unknown>
+
+th.vmsgt.vx v8, v4, a0
+# CHECK-INST: th.vmsgt.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 7e <unknown>
+
+th.vmsgt.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vmsgt.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 7c <unknown>
+
+th.vmsgt.vi v8, v4, 15
+# CHECK-INST: th.vmsgt.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 7e <unknown>
+
diff --git a/llvm/test/MC/RISCV/xtheadvector/convert.s b/llvm/test/MC/RISCV/xtheadvector/convert.s
new file mode 100644
index 00000000000000..af5ee9ec1f936a
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/convert.s
@@ -0,0 +1,186 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfcvt.xu.f.v v8, v4, v0.t
+# CHECK-INST: th.vfcvt.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x40,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 40 88 <unknown>
+
+th.vfcvt.xu.f.v v8, v4
+# CHECK-INST: th.vfcvt.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 40 8a <unknown>
+
+th.vfcvt.x.f.v v8, v4, v0.t
+# CHECK-INST: th.vfcvt.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x40,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 40 88 <unknown>
+
+th.vfcvt.x.f.v v8, v4
+# CHECK-INST: th.vfcvt.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x40,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 40 8a <unknown>
+
+th.vfcvt.f.xu.v v8, v4, v0.t
+# CHECK-INST: th.vfcvt.f.xu.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x41,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 41 88 <unknown>
+
+th.vfcvt.f.xu.v v8, v4
+# CHECK-INST: th.vfcvt.f.xu.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x41,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 41 8a <unknown>
+
+th.vfcvt.f.x.v v8, v4, v0.t
+# CHECK-INST: th.vfcvt.f.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x41,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 41 88 <unknown>
+
+th.vfcvt.f.x.v v8, v4
+# CHECK-INST: th.vfcvt.f.x.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x41,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 41 8a <unknown>
+
+th.vfwcvt.xu.f.v v8, v4, v0.t
+# CHECK-INST: th.vfwcvt.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x44,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 44 88 <unknown>
+
+th.vfwcvt.xu.f.v v8, v4
+# CHECK-INST: th.vfwcvt.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x44,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 44 8a <unknown>
+
+th.vfwcvt.x.f.v v8, v4, v0.t
+# CHECK-INST: th.vfwcvt.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x44,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 44 88 <unknown>
+
+th.vfwcvt.x.f.v v8, v4
+# CHECK-INST: th.vfwcvt.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x44,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 44 8a <unknown>
+
+th.vfwcvt.f.xu.v v8, v4, v0.t
+# CHECK-INST: th.vfwcvt.f.xu.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 45 88 <unknown>
+
+th.vfwcvt.f.xu.v v8, v4
+# CHECK-INST: th.vfwcvt.f.xu.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 45 8a <unknown>
+
+th.vfwcvt.f.x.v v8, v4, v0.t
+# CHECK-INST: th.vfwcvt.f.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 45 88 <unknown>
+
+th.vfwcvt.f.x.v v8, v4
+# CHECK-INST: th.vfwcvt.f.x.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 45 8a <unknown>
+
+th.vfwcvt.f.f.v v8, v4, v0.t
+# CHECK-INST: th.vfwcvt.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x46,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 46 88 <unknown>
+
+th.vfwcvt.f.f.v v8, v4
+# CHECK-INST: th.vfwcvt.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x46,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 46 8a <unknown>
+
+th.vfncvt.xu.f.v v8, v4, v0.t
+# CHECK-INST: th.vfncvt.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x48,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 48 88 <unknown>
+
+th.vfncvt.xu.f.v v4, v4, v0.t
+# CHECK-INST: th.vfncvt.xu.f.v v4, v4, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x48,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 12 48 88 <unknown>
+
+th.vfncvt.xu.f.v v8, v4
+# CHECK-INST: th.vfncvt.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 48 8a <unknown>
+
+th.vfncvt.x.f.v v8, v4, v0.t
+# CHECK-INST: th.vfncvt.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x48,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 48 88 <unknown>
+
+th.vfncvt.x.f.v v8, v4
+# CHECK-INST: th.vfncvt.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x48,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 48 8a <unknown>
+
+th.vfncvt.f.xu.v v8, v4, v0.t
+# CHECK-INST: th.vfncvt.f.xu.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x49,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 49 88 <unknown>
+
+th.vfncvt.f.xu.v v8, v4
+# CHECK-INST: th.vfncvt.f.xu.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x49,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 49 8a <unknown>
+
+th.vfncvt.f.x.v v8, v4, v0.t
+# CHECK-INST: th.vfncvt.f.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x49,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 49 88 <unknown>
+
+th.vfncvt.f.x.v v8, v4
+# CHECK-INST: th.vfncvt.f.x.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x49,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 94 49 8a <unknown>
+
+th.vfncvt.f.f.v v8, v4, v0.t
+# CHECK-INST: th.vfncvt.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 88 <unknown>
+
+th.vfncvt.f.f.v v8, v4
+# CHECK-INST: th.vfncvt.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8a <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/div.s b/llvm/test/MC/RISCV/xtheadvector/div.s
new file mode 100644
index 00000000000000..d8ea62af6a83cb
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/div.s
@@ -0,0 +1,105 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vdivu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vdivu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 80 <unknown>
+
+th.vdivu.vv v8, v4, v20
+# CHECK-INST: th.vdivu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 82 <unknown>
+
+th.vdivu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vdivu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 80 <unknown>
+
+th.vdivu.vx v8, v4, a0
+# CHECK-INST: th.vdivu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 82 <unknown>
+
+th.vdiv.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vdiv.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x84]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 84 <unknown>
+
+th.vdiv.vv v8, v4, v20
+# CHECK-INST: th.vdiv.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x86]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 86 <unknown>
+
+th.vdiv.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vdiv.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 84 <unknown>
+
+th.vdiv.vx v8, v4, a0
+# CHECK-INST: th.vdiv.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 86 <unknown>
+
+th.vremu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vremu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 88 <unknown>
+
+th.vremu.vv v8, v4, v20
+# CHECK-INST: th.vremu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 8a <unknown>
+
+th.vremu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vremu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 88 <unknown>
+
+th.vremu.vx v8, v4, a0
+# CHECK-INST: th.vremu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 8a <unknown>
+
+th.vrem.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vrem.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 8c <unknown>
+
+th.vrem.vv v8, v4, v20
+# CHECK-INST: th.vrem.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 8e <unknown>
+
+th.vrem.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vrem.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 8c <unknown>
+
+th.vrem.vx v8, v4, a0
+# CHECK-INST: th.vrem.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 8e <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fadd.s b/llvm/test/MC/RISCV/xtheadvector/fadd.s
new file mode 100644
index 00000000000000..45a1bc479cabba
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fadd.s
@@ -0,0 +1,84 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfadd.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 00 <unknown>
+
+th.vfadd.vv v8, v4, v20
+# CHECK-INST: th.vfadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 02 <unknown>
+
+th.vfadd.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfadd.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 00 <unknown>
+
+th.vfadd.vf v8, v4, fa0
+# CHECK-INST: th.vfadd.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 02 <unknown>
+
+th.vfwadd.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfwadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a c0 <unknown>
+
+th.vfwadd.vv v8, v4, v20
+# CHECK-INST: th.vfwadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a c2 <unknown>
+
+th.vfwadd.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfwadd.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 c0 <unknown>
+
+th.vfwadd.vf v8, v4, fa0
+# CHECK-INST: th.vfwadd.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 c2 <unknown>
+
+th.vfwadd.wv v8, v4, v20, v0.t
+# CHECK-INST: th.vfwadd.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a d0 <unknown>
+
+th.vfwadd.wv v8, v4, v20
+# CHECK-INST: th.vfwadd.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a d2 <unknown>
+
+th.vfwadd.wf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfwadd.wf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 d0 <unknown>
+
+th.vfwadd.wf v8, v4, fa0
+# CHECK-INST: th.vfwadd.wf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 d2 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fcompare.s b/llvm/test/MC/RISCV/xtheadvector/fcompare.s
new file mode 100644
index 00000000000000..c91a1c12b97f5a
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fcompare.s
@@ -0,0 +1,162 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmfeq.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmfeq.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 60 <unknown>
+
+th.vmfeq.vv v8, v4, v20
+# CHECK-INST: th.vmfeq.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 62 <unknown>
+
+th.vmfeq.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vmfeq.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 60 <unknown>
+
+th.vmfeq.vf v8, v4, fa0
+# CHECK-INST: th.vmfeq.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 62 <unknown>
+
+th.vmfne.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmfne.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 70 <unknown>
+
+th.vmfne.vv v8, v4, v20
+# CHECK-INST: th.vmfne.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 72 <unknown>
+
+th.vmfne.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vmfne.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x70]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 70 <unknown>
+
+th.vmfne.vf v8, v4, fa0
+# CHECK-INST: th.vmfne.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x72]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 72 <unknown>
+
+th.vmflt.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmflt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 6c <unknown>
+
+th.vmflt.vv v8, v4, v20
+# CHECK-INST: th.vmflt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 6e <unknown>
+
+th.vmflt.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vmflt.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 6c <unknown>
+
+th.vmflt.vf v8, v4, fa0
+# CHECK-INST: th.vmflt.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 6e <unknown>
+
+th.vmfle.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmfle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 64 <unknown>
+
+th.vmfle.vv v8, v4, v20
+# CHECK-INST: th.vmfle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 66 <unknown>
+
+th.vmfle.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vmfle.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 64 <unknown>
+
+th.vmfle.vf v8, v4, fa0
+# CHECK-INST: th.vmfle.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 66 <unknown>
+
+th.vmfgt.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vmfgt.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x74]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 74 <unknown>
+
+th.vmfgt.vf v8, v4, fa0
+# CHECK-INST: th.vmfgt.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x76]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 76 <unknown>
+
+th.vmfge.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vmfge.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 7c <unknown>
+
+th.vmfge.vf v8, v4, fa0
+# CHECK-INST: th.vmfge.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 7e <unknown>
+
+th.vmford.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmford.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x68]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 68 <unknown>
+
+th.vmford.vv v8, v4, v20
+# CHECK-INST: th.vmford.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 6a <unknown>
+
+th.vmford.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vmford.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x68]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 68 <unknown>
+
+th.vmford.vf v8, v4, fa0
+# CHECK-INST: th.vmford.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x6a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 6a <unknown>
+
+th.vmfeq.vv v0, v4, v20, v0.t
+# CHECK-INST: th.vmfeq.vv v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x10,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 10 4a 60 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fdiv.s b/llvm/test/MC/RISCV/xtheadvector/fdiv.s
new file mode 100644
index 00000000000000..2062a0355b9850
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fdiv.s
@@ -0,0 +1,48 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfdiv.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfdiv.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 80 <unknown>
+
+th.vfdiv.vv v8, v4, v20
+# CHECK-INST: th.vfdiv.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 82 <unknown>
+
+th.vfdiv.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfdiv.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 80 <unknown>
+
+th.vfdiv.vf v8, v4, fa0
+# CHECK-INST: th.vfdiv.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 82 <unknown>
+
+th.vfrdiv.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfrdiv.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 84 <unknown>
+
+th.vfrdiv.vf v8, v4, fa0
+# CHECK-INST: th.vfrdiv.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 86 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fminmax.s b/llvm/test/MC/RISCV/xtheadvector/fminmax.s
new file mode 100644
index 00000000000000..6feb8fb361bca1
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fminmax.s
@@ -0,0 +1,60 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfmin.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfmin.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x10]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 10 <unknown>
+
+th.vfmin.vv v8, v4, v20
+# CHECK-INST: th.vfmin.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x12]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 12 <unknown>
+
+th.vfmin.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfmin.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x10]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 10 <unknown>
+
+th.vfmin.vf v8, v4, fa0
+# CHECK-INST: th.vfmin.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x12]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 12 <unknown>
+
+th.vfmax.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfmax.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x18]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 18 <unknown>
+
+th.vfmax.vv v8, v4, v20
+# CHECK-INST: th.vfmax.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 1a <unknown>
+
+th.vfmax.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfmax.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x18]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 18 <unknown>
+
+th.vfmax.vf v8, v4, fa0
+# CHECK-INST: th.vfmax.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x1a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 1a <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fmul.s b/llvm/test/MC/RISCV/xtheadvector/fmul.s
new file mode 100644
index 00000000000000..0909cdc047b6a4
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fmul.s
@@ -0,0 +1,60 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfmul.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 90 <unknown>
+
+th.vfmul.vv v8, v4, v20
+# CHECK-INST: th.vfmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 92 <unknown>
+
+th.vfmul.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfmul.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x90]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 90 <unknown>
+
+th.vfmul.vf v8, v4, fa0
+# CHECK-INST: th.vfmul.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x92]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 92 <unknown>
+
+th.vfwmul.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfwmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xe0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a e0 <unknown>
+
+th.vfwmul.vv v8, v4, v20
+# CHECK-INST: th.vfwmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xe2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a e2 <unknown>
+
+th.vfwmul.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfwmul.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 e0 <unknown>
+
+th.vfwmul.vf v8, v4, fa0
+# CHECK-INST: th.vfwmul.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 e2 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fmv.s b/llvm/test/MC/RISCV/xtheadvector/fmv.s
new file mode 100644
index 00000000000000..dd30247b96810a
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fmv.s
@@ -0,0 +1,30 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfmv.v.f v8, fa0
+# CHECK-INST: th.vfmv.v.f v8, fa0
+# CHECK-ENCODING: [0x57,0x54,0x05,0x5e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 05 5e <unknown>
+
+th.vfmv.f.s fa0, v4
+# CHECK-INST: th.vfmv.f.s fa0, v4
+# CHECK-ENCODING: [0x57,0x15,0x40,0x32]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 15 40 32 <unknown>
+
+th.vfmv.s.f v8, fa0
+# CHECK-INST: th.vfmv.s.f v8, fa0
+# CHECK-ENCODING: [0x57,0x54,0x05,0x36]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 05 36 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fothers.s b/llvm/test/MC/RISCV/xtheadvector/fothers.s
new file mode 100644
index 00000000000000..c8ea8a6d173c6d
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fothers.s
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f --riscv-no-aliases \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f | llvm-objdump -d --mattr=+xtheadvector --mattr=+f -M no-aliases - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfsqrt.v v8, v4, v0.t
+# CHECK-INST: th.vfsqrt.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 40 8c <unknown>
+
+th.vfsqrt.v v8, v4
+# CHECK-INST: th.vfsqrt.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 40 8e <unknown>
+
+th.vfclass.v v8, v4, v0.t
+# CHECK-INST: th.vfclass.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 48 8c <unknown>
+
+th.vfclass.v v8, v4
+# CHECK-INST: th.vfclass.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 48 8e <unknown>
+
+th.vfmerge.vfm v8, v4, fa0, v0
+# CHECK-INST: th.vfmerge.vfm v8, v4, fa0, v0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 5c <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/freduction.s b/llvm/test/MC/RISCV/xtheadvector/freduction.s
new file mode 100644
index 00000000000000..39db3c113b10a5
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/freduction.s
@@ -0,0 +1,90 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f --riscv-no-aliases \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f \
+# RUN: -M no-aliases - | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfredosum.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vfredosum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 0c <unknown>
+
+th.vfredosum.vs v8, v4, v20
+# CHECK-INST: th.vfredosum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 0e <unknown>
+
+th.vfredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vfredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x04]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 04 <unknown>
+
+th.vfredsum.vs v8, v4, v20
+# CHECK-INST: th.vfredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x06]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 06 <unknown>
+
+th.vfredmax.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vfredmax.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 1c <unknown>
+
+th.vfredmax.vs v8, v4, v20
+# CHECK-INST: th.vfredmax.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 1e <unknown>
+
+th.vfredmin.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vfredmin.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x14]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 14 <unknown>
+
+th.vfredmin.vs v8, v4, v20
+# CHECK-INST: th.vfredmin.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x16]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 16 <unknown>
+
+th.vfwredosum.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vfwredosum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xcc]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a cc <unknown>
+
+th.vfwredosum.vs v8, v4, v20
+# CHECK-INST: th.vfwredosum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xce]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a ce <unknown>
+
+th.vfwredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vfwredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a c4 <unknown>
+
+th.vfwredsum.vs v8, v4, v20
+# CHECK-INST: th.vfwredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a c6 <unknown>
+
+th.vfredosum.vs v0, v4, v20, v0.t
+# CHECK-INST: th.vfredosum.vs v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x10,0x4a,0x0c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 10 4a 0c <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/fsub.s b/llvm/test/MC/RISCV/xtheadvector/fsub.s
new file mode 100644
index 00000000000000..5cc69d9a5d844f
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fsub.s
@@ -0,0 +1,96 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfsub.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x08]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 08 <unknown>
+
+th.vfsub.vv v8, v4, v20
+# CHECK-INST: th.vfsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 0a <unknown>
+
+th.vfsub.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfsub.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 08 <unknown>
+
+th.vfsub.vf v8, v4, fa0
+# CHECK-INST: th.vfsub.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 0a <unknown>
+
+th.vfrsub.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfrsub.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 9c <unknown>
+
+th.vfrsub.vf v8, v4, fa0
+# CHECK-INST: th.vfrsub.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 9e <unknown>
+
+th.vfwsub.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfwsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a c8 <unknown>
+
+th.vfwsub.vv v8, v4, v20
+# CHECK-INST: th.vfwsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xca]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a ca <unknown>
+
+th.vfwsub.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfwsub.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 c8 <unknown>
+
+th.vfwsub.vf v8, v4, fa0
+# CHECK-INST: th.vfwsub.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xca]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 ca <unknown>
+
+th.vfwsub.wv v8, v4, v20, v0.t
+# CHECK-INST: th.vfwsub.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a d8 <unknown>
+
+th.vfwsub.wv v8, v4, v20
+# CHECK-INST: th.vfwsub.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xda]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a da <unknown>
+
+th.vfwsub.wf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfwsub.wf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 d8 <unknown>
+
+th.vfwsub.wf v8, v4, fa0
+# CHECK-INST: th.vfwsub.wf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xda]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 da <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/load.s b/llvm/test/MC/RISCV/xtheadvector/load.s
new file mode 100644
index 00000000000000..3832152ffa8e2f
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/load.s
@@ -0,0 +1,345 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector -M no-aliases - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vlb.v v8, (a0), v0.t
+# CHECK-INST: th.vlb.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 10 <unknown>
+
+th.vlb.v v8, (a0)
+# CHECK-INST: th.vlb.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 12 <unknown>
+
+th.vlh.v v8, (a0), v0.t
+# CHECK-INST: th.vlh.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 10 <unknown>
+
+th.vlh.v v8, (a0)
+# CHECK-INST: th.vlh.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 12 <unknown>
+
+th.vlw.v v8, (a0), v0.t
+# CHECK-INST: th.vlw.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 10 <unknown>
+
+th.vlw.v v8, (a0)
+# CHECK-INST: th.vlw.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 12 <unknown>
+
+th.vlbu.v v8, (a0), v0.t
+# CHECK-INST: th.vlbu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 00 <unknown>
+
+th.vlbu.v v8, (a0)
+# CHECK-INST: th.vlbu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 02 <unknown>
+
+th.vlhu.v v8, (a0), v0.t
+# CHECK-INST: th.vlhu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 00 <unknown>
+
+th.vlhu.v v8, (a0)
+# CHECK-INST: th.vlhu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 02 <unknown>
+
+th.vlwu.v v8, (a0), v0.t
+# CHECK-INST: th.vlwu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 00 <unknown>
+
+th.vlwu.v v8, (a0)
+# CHECK-INST: th.vlwu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 02 <unknown>
+
+th.vle.v v8, (a0), v0.t
+# CHECK-INST: th.vle.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 00 <unknown>
+
+th.vle.v v8, (a0)
+# CHECK-INST: th.vle.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 02 <unknown>
+
+th.vlsb.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsb.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
+
+th.vlsb.v v8, (a0), a1
+# CHECK-INST: th.vlsb.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
+
+th.vlsh.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsh.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
+
+th.vlsh.v v8, (a0), a1
+# CHECK-INST: th.vlsh.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
+
+th.vlsw.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsw.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
+
+th.vlsw.v v8, (a0), a1
+# CHECK-INST: th.vlsw.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+
+th.vlsbu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsbu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 08 <unknown>
+
+th.vlsbu.v v8, (a0), a1
+# CHECK-INST: th.vlsbu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 0a <unknown>
+
+th.vlshu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlshu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 08 <unknown>
+
+th.vlshu.v v8, (a0), a1
+# CHECK-INST: th.vlshu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 0a <unknown>
+
+th.vlswu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlswu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 08 <unknown>
+
+th.vlswu.v v8, (a0), a1
+# CHECK-INST: th.vlswu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 0a <unknown>
+
+th.vlse.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlse.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 08 <unknown>
+
+th.vlse.v v8, (a0), a1
+# CHECK-INST: th.vlse.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 0a <unknown>
+
+th.vlxb.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxb.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+
+th.vlxb.v v8, (a0), v4
+# CHECK-INST: th.vlxb.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+
+th.vlxh.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxh.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+
+th.vlxh.v v8, (a0), v4
+# CHECK-INST: th.vlxh.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+
+th.vlxw.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxw.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+
+th.vlxw.v v8, (a0), v4
+# CHECK-INST: th.vlxw.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+
+th.vlxbu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxbu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 0c <unknown>
+
+th.vlxbu.v v8, (a0), v4
+# CHECK-INST: th.vlxbu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 0e <unknown>
+
+th.vlxhu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxhu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 0c <unknown>
+
+th.vlxhu.v v8, (a0), v4
+# CHECK-INST: th.vlxhu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 0e <unknown>
+
+th.vlxwu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxwu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 0c <unknown>
+
+th.vlxwu.v v8, (a0), v4
+# CHECK-INST: th.vlxwu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 0e <unknown>
+
+th.vlxe.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxe.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 0c <unknown>
+
+th.vlxe.v v8, (a0), v4
+# CHECK-INST: th.vlxe.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 0e <unknown>
+
+th.vlbff.v v8, (a0)
+# CHECK-INST: th.vlbff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 13 <unknown>
+
+th.vlbff.v v8, (a0), v0.t
+# CHECK-INST: th.vlbff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 11 <unknown>
+
+th.vlhff.v v8, (a0)
+# CHECK-INST: th.vlhff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 13 <unknown>
+
+th.vlhff.v v8, (a0), v0.t
+# CHECK-INST: th.vlhff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 11 <unknown>
+
+th.vlwff.v v8, (a0)
+# CHECK-INST: th.vlwff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+
+th.vlwff.v v8, (a0), v0.t
+# CHECK-INST: th.vlwff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 11 <unknown>
+
+th.vlbuff.v v8, (a0)
+# CHECK-INST: th.vlbuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 03 <unknown>
+
+th.vlbuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlbuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 01 <unknown>
+
+th.vlhuff.v v8, (a0)
+# CHECK-INST: th.vlhuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 03 <unknown>
+
+th.vlhuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlhuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 01 <unknown>
+
+th.vlwuff.v v8, (a0)
+# CHECK-INST: th.vlwuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 03 <unknown>
+
+th.vlwuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlwuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 01 <unknown>
+
+th.vleff.v v8, (a0)
+# CHECK-INST: th.vleff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 03 <unknown>
+
+th.vleff.v v8, (a0), v0.t
+# CHECK-INST: th.vleff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 01 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/mask.s b/llvm/test/MC/RISCV/xtheadvector/mask.s
new file mode 100644
index 00000000000000..5a74807d46ef34
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/mask.s
@@ -0,0 +1,141 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmand.mm v8, v4, v20
+# CHECK-INST: th.vmand.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 66 <unknown>
+
+th.vmnand.mm v8, v4, v20
+# CHECK-INST: th.vmnand.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x76]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 76 <unknown>
+
+th.vmandnot.mm v8, v4, v20
+# CHECK-INST: th.vmandnot.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 62 <unknown>
+
+th.vmxor.mm v8, v4, v20
+# CHECK-INST: th.vmxor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 6e <unknown>
+
+th.vmor.mm v8, v4, v20
+# CHECK-INST: th.vmor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 6a <unknown>
+
+th.vmnor.mm v8, v4, v20
+# CHECK-INST: th.vmnor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x7a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 7a <unknown>
+
+th.vmornot.mm v8, v4, v20
+# CHECK-INST: th.vmornot.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 72 <unknown>
+
+th.vmxnor.mm v8, v4, v20
+# CHECK-INST: th.vmxnor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x7e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 7e <unknown>
+
+th.vmpopc.m a2, v4, v0.t
+# CHECK-INST: th.vmpopc.m a2, v4, v0.t
+# CHECK-ENCODING: [0x57,0x26,0x40,0x50]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 26 40 50 <unknown>
+
+th.vmpopc.m a2, v4
+# CHECK-INST: th.vmpopc.m a2, v4
+# CHECK-ENCODING: [0x57,0x26,0x40,0x52]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 26 40 52 <unknown>
+
+th.vmfirst.m a2, v4, v0.t
+# CHECK-INST: th.vmfirst.m a2, v4, v0.t
+# CHECK-ENCODING: [0x57,0x26,0x40,0x54]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 26 40 54 <unknown>
+
+th.vmfirst.m a2, v4
+# CHECK-INST: th.vmfirst.m a2, v4
+# CHECK-ENCODING: [0x57,0x26,0x40,0x56]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 26 40 56 <unknown>
+
+th.vmsbf.m v8, v4, v0.t
+# CHECK-INST: th.vmsbf.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x40,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 a4 40 58 <unknown>
+
+th.vmsbf.m v8, v4
+# CHECK-INST: th.vmsbf.m v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x40,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 a4 40 5a <unknown>
+
+th.vmsif.m v8, v4, v0.t
+# CHECK-INST: th.vmsif.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 a4 41 58 <unknown>
+
+th.vmsif.m v8, v4
+# CHECK-INST: th.vmsif.m v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 a4 41 5a <unknown>
+
+th.vmsof.m v8, v4, v0.t
+# CHECK-INST: th.vmsof.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x41,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 41 58 <unknown>
+
+th.vmsof.m v8, v4
+# CHECK-INST: th.vmsof.m v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x41,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 41 5a <unknown>
+
+th.viota.m v8, v4, v0.t
+# CHECK-INST: th.viota.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x48,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 48 58 <unknown>
+
+th.viota.m v8, v4
+# CHECK-INST: th.viota.m v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x48,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 48 5a <unknown>
+
+th.vid.v v8, v0.t
+# CHECK-INST: th.vid.v v8, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x08,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 a4 08 58 <unknown>
+
+th.vid.v v8
+# CHECK-INST: th.vid.v v8
+# CHECK-ENCODING: [0x57,0xa4,0x08,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 a4 08 5a <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/minmax.s b/llvm/test/MC/RISCV/xtheadvector/minmax.s
new file mode 100644
index 00000000000000..a406cd16ccfe0d
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/minmax.s
@@ -0,0 +1,105 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vminu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vminu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x10]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 10 <unknown>
+
+th.vminu.vv v8, v4, v20
+# CHECK-INST: th.vminu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x12]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 12 <unknown>
+
+th.vminu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vminu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x10]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 10 <unknown>
+
+th.vminu.vx v8, v4, a0
+# CHECK-INST: th.vminu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x12]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 12 <unknown>
+
+th.vmin.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmin.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x14]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 14 <unknown>
+
+th.vmin.vv v8, v4, v20
+# CHECK-INST: th.vmin.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x16]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 16 <unknown>
+
+th.vmin.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmin.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x14]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 14 <unknown>
+
+th.vmin.vx v8, v4, a0
+# CHECK-INST: th.vmin.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x16]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 16 <unknown>
+
+th.vmaxu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmaxu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x18]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 18 <unknown>
+
+th.vmaxu.vv v8, v4, v20
+# CHECK-INST: th.vmaxu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x1a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 1a <unknown>
+
+th.vmaxu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmaxu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x18]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 18 <unknown>
+
+th.vmaxu.vx v8, v4, a0
+# CHECK-INST: th.vmaxu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x1a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 1a <unknown>
+
+th.vmax.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmax.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 1c <unknown>
+
+th.vmax.vv v8, v4, v20
+# CHECK-INST: th.vmax.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 1e <unknown>
+
+th.vmax.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmax.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 1c <unknown>
+
+th.vmax.vx v8, v4, a0
+# CHECK-INST: th.vmax.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 1e <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/mul.s b/llvm/test/MC/RISCV/xtheadvector/mul.s
new file mode 100644
index 00000000000000..fecb361dcc5335
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/mul.s
@@ -0,0 +1,201 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmul.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x94]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 94 <unknown>
+
+th.vmul.vv v8, v4, v20
+# CHECK-INST: th.vmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x96]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 96 <unknown>
+
+th.vmul.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmul.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x94]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 94 <unknown>
+
+th.vmul.vx v8, v4, a0
+# CHECK-INST: th.vmul.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x96]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 96 <unknown>
+
+th.vmulh.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmulh.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 9c <unknown>
+
+th.vmulh.vv v8, v4, v20
+# CHECK-INST: th.vmulh.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 9e <unknown>
+
+th.vmulh.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmulh.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 9c <unknown>
+
+th.vmulh.vx v8, v4, a0
+# CHECK-INST: th.vmulh.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 9e <unknown>
+
+th.vmulhu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmulhu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 90 <unknown>
+
+th.vmulhu.vv v8, v4, v20
+# CHECK-INST: th.vmulhu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 92 <unknown>
+
+th.vmulhu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmulhu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 90 <unknown>
+
+th.vmulhu.vx v8, v4, a0
+# CHECK-INST: th.vmulhu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 92 <unknown>
+
+th.vmulhsu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vmulhsu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x98]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 98 <unknown>
+
+th.vmulhsu.vv v8, v4, v20
+# CHECK-INST: th.vmulhsu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 9a <unknown>
+
+th.vmulhsu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vmulhsu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x98]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 98 <unknown>
+
+th.vmulhsu.vx v8, v4, a0
+# CHECK-INST: th.vmulhsu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 9a <unknown>
+
+th.vwmul.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vwmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a ec <unknown>
+
+th.vwmul.vv v8, v4, v20
+# CHECK-INST: th.vwmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a ee <unknown>
+
+th.vwmul.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vwmul.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 ec <unknown>
+
+th.vwmul.vx v8, v4, a0
+# CHECK-INST: th.vwmul.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 ee <unknown>
+
+th.vwmulu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vwmulu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a e0 <unknown>
+
+th.vwmulu.vv v8, v4, v20
+# CHECK-INST: th.vwmulu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a e2 <unknown>
+
+th.vwmulu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vwmulu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 e0 <unknown>
+
+th.vwmulu.vx v8, v4, a0
+# CHECK-INST: th.vwmulu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 e2 <unknown>
+
+th.vwmulsu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vwmulsu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a e8 <unknown>
+
+th.vwmulsu.vv v8, v4, v20
+# CHECK-INST: th.vwmulsu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a ea <unknown>
+
+th.vwmulsu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vwmulsu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 e8 <unknown>
+
+th.vwmulsu.vx v8, v4, a0
+# CHECK-INST: th.vwmulsu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 ea <unknown>
+
+th.vsmul.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vsmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 9c <unknown>
+
+th.vsmul.vv v8, v4, v20
+# CHECK-INST: th.vsmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 9e <unknown>
+
+th.vsmul.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vsmul.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 9c <unknown>
+
+th.vsmul.vx v8, v4, a0
+# CHECK-INST: th.vsmul.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 9e <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/mv.s b/llvm/test/MC/RISCV/xtheadvector/mv.s
new file mode 100644
index 00000000000000..f20770db12fbf4
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/mv.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmv.v.v v8, v20
+# CHECK-INST: th.vmv.v.v v8, v20
+# CHECK-ENCODING: [0x57,0x04,0x0a,0x5e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 0a 5e <unknown>
+
+th.vmv.v.x v8, a0
+# CHECK-INST: th.vmv.v.x v8, a0
+# CHECK-ENCODING: [0x57,0x44,0x05,0x5e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 05 5e <unknown>
+
+th.vmv.v.i v8, 15
+# CHECK-INST: th.vmv.v.i v8, 15
+# CHECK-ENCODING: [0x57,0xb4,0x07,0x5e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 07 5e <unknown>
+
+th.vext.x.v a2, v4, a0
+# CHECK-INST: th.vext.x.v a2, v4, a0
+# CHECK-ENCODING: [0x57,0x26,0x45,0x32]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 26 45 32 <unknown>
+
+th.vmv.s.x v8, a0
+# CHECK-INST: th.vmv.s.x v8, a0
+# CHECK-ENCODING: [0x57,0x64,0x05,0x36]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 05 36 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/or.s b/llvm/test/MC/RISCV/xtheadvector/or.s
new file mode 100644
index 00000000000000..e215453ecbac3a
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/or.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vor.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vor.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 28 <unknown>
+
+th.vor.vv v8, v4, v20
+# CHECK-INST: th.vor.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 2a <unknown>
+
+th.vor.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vor.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 28 <unknown>
+
+th.vor.vx v8, v4, a0
+# CHECK-INST: th.vor.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 2a <unknown>
+
+th.vor.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vor.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 28 <unknown>
+
+th.vor.vi v8, v4, 15
+# CHECK-INST: th.vor.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 2a <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/others.s b/llvm/test/MC/RISCV/xtheadvector/others.s
new file mode 100644
index 00000000000000..6ff5ab3e025e3f
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/others.s
@@ -0,0 +1,138 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmerge.vvm v8, v4, v20, v0
+# CHECK-INST: th.vmerge.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x5c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 5c <unknown>
+
+th.vmerge.vxm v8, v4, a0, v0
+# CHECK-INST: th.vmerge.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 5c <unknown>
+
+th.vmerge.vim v8, v4, 15, v0
+# CHECK-INST: th.vmerge.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x5c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 5c <unknown>
+
+th.vslideup.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vslideup.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x38]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 38 <unknown>
+
+th.vslideup.vx v8, v4, a0
+# CHECK-INST: th.vslideup.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x3a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 3a <unknown>
+
+th.vslideup.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vslideup.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x38]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 38 <unknown>
+
+th.vslideup.vi v8, v4, 31
+# CHECK-INST: th.vslideup.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 3a <unknown>
+
+th.vslidedown.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vslidedown.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 3c <unknown>
+
+th.vslidedown.vx v8, v4, a0
+# CHECK-INST: th.vslidedown.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 3e <unknown>
+
+th.vslidedown.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vslidedown.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 3c <unknown>
+
+th.vslidedown.vi v8, v4, 31
+# CHECK-INST: th.vslidedown.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 3e <unknown>
+
+th.vslide1up.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vslide1up.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x38]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 38 <unknown>
+
+th.vslide1up.vx v8, v4, a0
+# CHECK-INST: th.vslide1up.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x3a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 3a <unknown>
+
+th.vslide1down.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vslide1down.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 3c <unknown>
+
+th.vslide1down.vx v8, v4, a0
+# CHECK-INST: th.vslide1down.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 3e <unknown>
+
+th.vrgather.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vrgather.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x30]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 30 <unknown>
+
+th.vrgather.vv v8, v4, v20
+# CHECK-INST: th.vrgather.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x32]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 32 <unknown>
+
+th.vrgather.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vrgather.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x30]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 30 <unknown>
+
+th.vrgather.vx v8, v4, a0
+# CHECK-INST: th.vrgather.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x32]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 32 <unknown>
+
+th.vrgather.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vrgather.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x30]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 30 <unknown>
+
+th.vrgather.vi v8, v4, 31
+# CHECK-INST: th.vrgather.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x32]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 32 <unknown>
+
+th.vcompress.vm v8, v4, v20
+# CHECK-INST: th.vcompress.vm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x5e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 5e <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/reduction.s b/llvm/test/MC/RISCV/xtheadvector/reduction.s
new file mode 100644
index 00000000000000..2580de7827a5c3
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/reduction.s
@@ -0,0 +1,135 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 00 <unknown>
+
+th.vredsum.vs v8, v4, v20
+# CHECK-INST: th.vredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 02 <unknown>
+
+th.vredmaxu.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredmaxu.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x18]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 18 <unknown>
+
+th.vredmaxu.vs v8, v4, v20
+# CHECK-INST: th.vredmaxu.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x1a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 1a <unknown>
+
+th.vredmax.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredmax.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 1c <unknown>
+
+th.vredmax.vs v8, v4, v20
+# CHECK-INST: th.vredmax.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 1e <unknown>
+
+th.vredminu.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredminu.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x10]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 10 <unknown>
+
+th.vredminu.vs v8, v4, v20
+# CHECK-INST: th.vredminu.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x12]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 12 <unknown>
+
+th.vredmin.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredmin.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x14]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 14 <unknown>
+
+th.vredmin.vs v8, v4, v20
+# CHECK-INST: th.vredmin.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x16]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 16 <unknown>
+
+th.vredand.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredand.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x04]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 04 <unknown>
+
+th.vredand.vs v8, v4, v20
+# CHECK-INST: th.vredand.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x06]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 06 <unknown>
+
+th.vredor.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredor.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 08 <unknown>
+
+th.vredor.vs v8, v4, v20
+# CHECK-INST: th.vredor.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 0a <unknown>
+
+th.vredxor.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vredxor.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 0c <unknown>
+
+th.vredxor.vs v8, v4, v20
+# CHECK-INST: th.vredxor.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a 0e <unknown>
+
+th.vwredsumu.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vwredsumu.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a c0 <unknown>
+
+th.vwredsumu.vs v8, v4, v20
+# CHECK-INST: th.vwredsumu.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a c2 <unknown>
+
+th.vwredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: th.vwredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a c4 <unknown>
+
+th.vwredsum.vs v8, v4, v20
+# CHECK-INST: th.vwredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a c6 <unknown>
+
+th.vredsum.vs v0, v4, v20, v0.t
+# CHECK-INST: th.vredsum.vs v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x20,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 20 4a 00 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/shift.s b/llvm/test/MC/RISCV/xtheadvector/shift.s
new file mode 100644
index 00000000000000..eee3b1eeb8c71b
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/shift.s
@@ -0,0 +1,264 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vsll.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vsll.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x94]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 94 <unknown>
+
+th.vsll.vv v8, v4, v20
+# CHECK-INST: th.vsll.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x96]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 96 <unknown>
+
+th.vsll.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vsll.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x94]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 94 <unknown>
+
+th.vsll.vx v8, v4, a0
+# CHECK-INST: th.vsll.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x96]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 96 <unknown>
+
+th.vsll.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vsll.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x94]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 94 <unknown>
+
+th.vsll.vi v8, v4, 31
+# CHECK-INST: th.vsll.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x96]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f 96 <unknown>
+
+th.vsrl.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vsrl.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a a0 <unknown>
+
+th.vsrl.vv v8, v4, v20
+# CHECK-INST: th.vsrl.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a a2 <unknown>
+
+th.vsrl.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vsrl.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 a0 <unknown>
+
+th.vsrl.vx v8, v4, a0
+# CHECK-INST: th.vsrl.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 a2 <unknown>
+
+th.vsrl.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vsrl.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f a0 <unknown>
+
+th.vsrl.vi v8, v4, 31
+# CHECK-INST: th.vsrl.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f a2 <unknown>
+
+th.vsra.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vsra.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a a4 <unknown>
+
+th.vsra.vv v8, v4, v20
+# CHECK-INST: th.vsra.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a a6 <unknown>
+
+th.vsra.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vsra.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 a4 <unknown>
+
+th.vsra.vx v8, v4, a0
+# CHECK-INST: th.vsra.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 a6 <unknown>
+
+th.vsra.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vsra.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f a4 <unknown>
+
+th.vsra.vi v8, v4, 31
+# CHECK-INST: th.vsra.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f a6 <unknown>
+
+th.vnsrl.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vnsrl.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a b0 <unknown>
+
+th.vnsrl.vv v4, v4, v20, v0.t
+# CHECK-INST: th.vnsrl.vv v4, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 02 4a b0 <unknown>
+
+th.vnsrl.vv v8, v4, v20
+# CHECK-INST: th.vnsrl.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a b2 <unknown>
+
+th.vnsrl.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vnsrl.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 b0 <unknown>
+
+th.vnsrl.vx v8, v4, a0
+# CHECK-INST: th.vnsrl.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 b2 <unknown>
+
+th.vnsrl.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vnsrl.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f b0 <unknown>
+
+th.vnsrl.vi v8, v4, 31
+# CHECK-INST: th.vnsrl.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f b2 <unknown>
+
+th.vnsra.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vnsra.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a b4 <unknown>
+
+th.vnsra.vv v8, v4, v20
+# CHECK-INST: th.vnsra.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a b6 <unknown>
+
+th.vnsra.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vnsra.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 b4 <unknown>
+
+th.vnsra.vx v8, v4, a0
+# CHECK-INST: th.vnsra.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 b6 <unknown>
+
+th.vnsra.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vnsra.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f b4 <unknown>
+
+th.vnsra.vi v8, v4, 31
+# CHECK-INST: th.vnsra.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f b6 <unknown>
+
+th.vssrl.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vssrl.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a a8 <unknown>
+
+th.vssrl.vv v8, v4, v20
+# CHECK-INST: th.vssrl.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a aa <unknown>
+
+th.vssrl.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vssrl.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 a8 <unknown>
+
+th.vssrl.vx v8, v4, a0
+# CHECK-INST: th.vssrl.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 aa <unknown>
+
+th.vssrl.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vssrl.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f a8 <unknown>
+
+th.vssrl.vi v8, v4, 31
+# CHECK-INST: th.vssrl.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f aa <unknown>
+
+th.vssra.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vssra.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a ac <unknown>
+
+th.vssra.vv v8, v4, v20
+# CHECK-INST: th.vssra.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a ae <unknown>
+
+th.vssra.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vssra.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 ac <unknown>
+
+th.vssra.vx v8, v4, a0
+# CHECK-INST: th.vssra.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 ae <unknown>
+
+th.vssra.vi v8, v4, 31, v0.t
+# CHECK-INST: th.vssra.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f ac <unknown>
+
+th.vssra.vi v8, v4, 31
+# CHECK-INST: th.vssra.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 4f ae <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/sign-injection.s b/llvm/test/MC/RISCV/xtheadvector/sign-injection.s
new file mode 100644
index 00000000000000..43a970115f0802
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/sign-injection.s
@@ -0,0 +1,84 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfsgnj.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfsgnj.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x20]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 20 <unknown>
+
+th.vfsgnj.vv v8, v4, v20
+# CHECK-INST: th.vfsgnj.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x22]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 22 <unknown>
+
+th.vfsgnj.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfsgnj.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 20 <unknown>
+
+th.vfsgnj.vf v8, v4, fa0
+# CHECK-INST: th.vfsgnj.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 22 <unknown>
+
+th.vfsgnjn.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfsgnjn.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x24]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 24 <unknown>
+
+th.vfsgnjn.vv v8, v4, v20
+# CHECK-INST: th.vfsgnjn.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x26]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 26 <unknown>
+
+th.vfsgnjn.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfsgnjn.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 24 <unknown>
+
+th.vfsgnjn.vf v8, v4, fa0
+# CHECK-INST: th.vfsgnjn.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 26 <unknown>
+
+th.vfsgnjx.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vfsgnjx.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x28]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 28 <unknown>
+
+th.vfsgnjx.vv v8, v4, v20
+# CHECK-INST: th.vfsgnjx.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x2a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a 2a <unknown>
+
+th.vfsgnjx.vf v8, v4, fa0, v0.t
+# CHECK-INST: th.vfsgnjx.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x28]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 28 <unknown>
+
+th.vfsgnjx.vf v8, v4, fa0
+# CHECK-INST: th.vfsgnjx.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x2a]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 2a <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/store.s b/llvm/test/MC/RISCV/xtheadvector/store.s
new file mode 100644
index 00000000000000..0945c46ed1ae91
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/store.s
@@ -0,0 +1,201 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector -M no-aliases - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vsb.v v8, (a0), v0.t
+# CHECK-INST: th.vsb.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 00 <unknown>
+
+th.vsb.v v8, (a0)
+# CHECK-INST: th.vsb.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 02 <unknown>
+
+th.vsh.v v8, (a0), v0.t
+# CHECK-INST: th.vsh.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 00 <unknown>
+
+th.vsh.v v8, (a0)
+# CHECK-INST: th.vsh.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 02 <unknown>
+
+th.vsw.v v8, (a0), v0.t
+# CHECK-INST: th.vsw.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 00 <unknown>
+
+th.vsw.v v8, (a0)
+# CHECK-INST: th.vsw.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 02 <unknown>
+
+th.vse.v v8, (a0), v0.t
+# CHECK-INST: th.vse.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 00 <unknown>
+
+th.vse.v v8, (a0)
+# CHECK-INST: th.vse.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 02 <unknown>
+
+th.vssb.v v8, (a0), a1
+# CHECK-INST: th.vssb.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 0a <unknown>
+
+th.vssb.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssb.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 08 <unknown>
+
+th.vssh.v v8, (a0), a1
+# CHECK-INST: th.vssh.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 0a <unknown>
+
+th.vssh.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssh.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 08 <unknown>
+
+th.vssw.v v8, (a0), a1
+# CHECK-INST: th.vssw.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 0a <unknown>
+
+th.vssw.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssw.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 08 <unknown>
+
+th.vsse.v v8, (a0), a1
+# CHECK-INST: th.vsse.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 0a <unknown>
+
+th.vsse.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vsse.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 08 <unknown>
+
+th.vsxb.v v8, (a0), v4
+# CHECK-INST: th.vsxb.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 0e <unknown>
+
+th.vsxb.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxb.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 0c <unknown>
+
+th.vsxh.v v8, (a0), v4
+# CHECK-INST: th.vsxh.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 0e <unknown>
+
+th.vsxh.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxh.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 0c <unknown>
+
+th.vsxw.v v8, (a0), v4
+# CHECK-INST: th.vsxw.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 0e <unknown>
+
+th.vsxw.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxw.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 0c <unknown>
+
+th.vsxe.v v8, (a0), v4
+# CHECK-INST: th.vsxe.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 0e <unknown>
+
+th.vsxe.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxe.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 0c <unknown>
+
+th.vsuxb.v v8, (a0), v4
+# CHECK-INST: th.vsuxb.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 1e <unknown>
+
+th.vsuxb.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsuxb.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 1c <unknown>
+
+th.vsuxh.v v8, (a0), v4
+# CHECK-INST: th.vsuxh.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 1e <unknown>
+
+th.vsuxh.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsuxh.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 1c <unknown>
+
+th.vsuxw.v v8, (a0), v4
+# CHECK-INST: th.vsuxw.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 1e <unknown>
+
+th.vsuxw.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsuxw.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 1c <unknown>
+
+th.vsuxe.v v8, (a0), v4
+# CHECK-INST: th.vsuxe.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 1e <unknown>
+
+th.vsuxe.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsuxe.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 1c <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/sub.s b/llvm/test/MC/RISCV/xtheadvector/sub.s
new file mode 100644
index 00000000000000..7d65ad92175b5c
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/sub.s
@@ -0,0 +1,270 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vsub.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 08 <unknown>
+
+th.vsub.vv v8, v4, v20
+# CHECK-INST: th.vsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 0a <unknown>
+
+th.vsub.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vsub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 08 <unknown>
+
+th.vsub.vx v8, v4, a0
+# CHECK-INST: th.vsub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 0a <unknown>
+
+th.vrsub.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vrsub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 0c <unknown>
+
+th.vrsub.vx v8, v4, a0
+# CHECK-INST: th.vrsub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 0e <unknown>
+
+th.vrsub.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vrsub.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x0c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 0c <unknown>
+
+th.vrsub.vi v8, v4, 15
+# CHECK-INST: th.vrsub.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x0e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 0e <unknown>
+
+th.vwsubu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vwsubu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a c8 <unknown>
+
+th.vwsubu.vv v8, v4, v20
+# CHECK-INST: th.vwsubu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a ca <unknown>
+
+th.vwsubu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vwsubu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 c8 <unknown>
+
+th.vwsubu.vx v8, v4, a0
+# CHECK-INST: th.vwsubu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 ca <unknown>
+
+th.vwsub.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vwsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a cc <unknown>
+
+th.vwsub.vv v8, v4, v20
+# CHECK-INST: th.vwsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a ce <unknown>
+
+th.vwsub.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vwsub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 cc <unknown>
+
+th.vwsub.vx v8, v4, a0
+# CHECK-INST: th.vwsub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 ce <unknown>
+
+th.vwsubu.wv v8, v4, v20, v0.t
+# CHECK-INST: th.vwsubu.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a d8 <unknown>
+
+th.vwsubu.wv v8, v4, v20
+# CHECK-INST: th.vwsubu.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xda]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a da <unknown>
+
+th.vwsubu.wx v8, v4, a0, v0.t
+# CHECK-INST: th.vwsubu.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 d8 <unknown>
+
+th.vwsubu.wx v8, v4, a0
+# CHECK-INST: th.vwsubu.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xda]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 da <unknown>
+
+th.vwsub.wv v8, v4, v20, v0.t
+# CHECK-INST: th.vwsub.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xdc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a dc <unknown>
+
+th.vwsub.wv v8, v4, v20
+# CHECK-INST: th.vwsub.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xde]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a de <unknown>
+
+th.vwsub.wx v8, v4, a0, v0.t
+# CHECK-INST: th.vwsub.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 dc <unknown>
+
+th.vwsub.wx v8, v4, a0
+# CHECK-INST: th.vwsub.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 de <unknown>
+
+th.vsbc.vvm v8, v4, v20, v0
+# CHECK-INST: th.vsbc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 4a <unknown>
+
+th.vsbc.vvm v4, v4, v20, v0
+# CHECK-INST: th.vsbc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 02 4a 4a <unknown>
+
+th.vsbc.vvm v8, v4, v8, v0
+# CHECK-INST: th.vsbc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 44 4a <unknown>
+
+th.vsbc.vxm v8, v4, a0, v0
+# CHECK-INST: th.vsbc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 4a <unknown>
+
+th.vmsbc.vvm v8, v4, v20, v0
+# CHECK-INST: th.vmsbc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 4e <unknown>
+
+th.vmsbc.vvm v4, v4, v20, v0
+# CHECK-INST: th.vmsbc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 02 4a 4e <unknown>
+
+th.vmsbc.vvm v8, v4, v8, v0
+# CHECK-INST: th.vmsbc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 44 4e <unknown>
+
+th.vmsbc.vxm v8, v4, a0, v0
+# CHECK-INST: th.vmsbc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 4e <unknown>
+
+th.vssubu.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vssubu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 88 <unknown>
+
+th.vssubu.vv v8, v4, v20
+# CHECK-INST: th.vssubu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 8a <unknown>
+
+th.vssubu.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vssubu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 88 <unknown>
+
+th.vssubu.vx v8, v4, a0
+# CHECK-INST: th.vssubu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 8a <unknown>
+
+th.vssub.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vssub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 8c <unknown>
+
+th.vssub.vv v8, v4, v20
+# CHECK-INST: th.vssub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 8e <unknown>
+
+th.vssub.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vssub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 8c <unknown>
+
+th.vssub.vx v8, v4, a0
+# CHECK-INST: th.vssub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 8e <unknown>
+
+th.vasub.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vasub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x98]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 98 <unknown>
+
+th.vasub.vv v8, v4, v20
+# CHECK-INST: th.vasub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x9a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 9a <unknown>
+
+th.vasub.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vasub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x98]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 98 <unknown>
+
+th.vasub.vx v8, v4, a0
+# CHECK-INST: th.vasub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x9a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 9a <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/vsetvl-invaild.s b/llvm/test/MC/RISCV/xtheadvector/vsetvl-invaild.s
new file mode 100644
index 00000000000000..8c7f2a1305f9d6
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/vsetvl-invaild.s
@@ -0,0 +1,15 @@
+# RUN: not llvm-mc -triple=riscv32 -show-encoding --mattr=+xtheadvector %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s 2>&1 | FileCheck %s
+
+th.vsetvli a2, a1, e8
+# CHECK: error: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|8] for XTHeadVector
+
+vsetivli a2, 15, 208
+# CHECK: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+
+vsetivli a2, 0, e32, m1, ta, ma
+# CHECK: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+
+vsetivli a2, 0, e32, m1, d1
+# CHECK: error: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
diff --git a/llvm/test/MC/RISCV/xtheadvector/vsetvl.s b/llvm/test/MC/RISCV/xtheadvector/vsetvl.s
new file mode 100644
index 00000000000000..b865bdbd39a49d
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/vsetvl.s
@@ -0,0 +1,118 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# reserved filed: vsew[2:0]=0b1xx, non-zero bits 8/9/10.
+th.vsetvli a2, a0, 0x224
+# CHECK-INST: th.vsetvli a2, a0, 548
+# CHECK-ENCODING: [0x57,0x76,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 45 22 <unknown>
+
+th.vsetvli a2, a0, 0x8
+# CHECK-INST: th.vsetvli a2, a0, e32, m1, d1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 85 00 <unknown>
+
+th.vsetvli a2, a0, 0x29
+# CHECK-INST: th.vsetvli a2, a0, e32, m2, d2
+# CHECK-ENCODING: [0x57,0x76,0x95,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 95 02 <unknown>
+
+th.vsetvli a2, a0, 0x4a
+# CHECK-INST: th.vsetvli a2, a0, e32, m4, d4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x04]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 a5 04 <unknown>
+
+th.vsetvli a2, a0, 0x6b
+# CHECK-INST: th.vsetvli a2, a0, e32, m8, d8
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x06]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 b5 06 <unknown>
+
+th.vsetvli a2, a0, 104
+# CHECK-INST: th.vsetvli a2, a0, e32, m1, d8
+# CHECK-ENCODING: [0x57,0x76,0x85,0x06]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 85 06 <unknown>
+
+th.vsetvli a2, a0, e32, m1, d1
+# CHECK-INST: th.vsetvli a2, a0, e32, m1, d1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 85 00 <unknown>
+
+th.vsetvli a2, a0, e32, m2, d2
+# CHECK-INST: th.vsetvli a2, a0, e32, m2, d2
+# CHECK-ENCODING: [0x57,0x76,0x95,0x02]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 95 02 <unknown>
+
+th.vsetvli a2, a0, e32, m4, d4
+# CHECK-INST: th.vsetvli a2, a0, e32, m4, d4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x04]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 a5 04 <unknown>
+
+th.vsetvli a2, a0, e32, m8, d8
+# CHECK-INST: th.vsetvli a2, a0, e32, m8, d8
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x06]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 b5 06 <unknown>
+
+th.vsetvli a2, a0, e32, m2, d1
+# CHECK-INST: th.vsetvli a2, a0, e32, m2, d1
+# CHECK-ENCODING: [0x57,0x76,0x95,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 95 00 <unknown>
+
+th.vsetvli a2, a0, e32, m4, d1
+# CHECK-INST: th.vsetvli a2, a0, e32, m4, d1
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 a5 00 <unknown>
+
+th.vsetvli a2, a0, e32, m8, d1
+# CHECK-INST: th.vsetvli a2, a0, e32, m8, d1
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 b5 00 <unknown>
+
+th.vsetvli a2, a0, e8, m1, d1
+# CHECK-INST: th.vsetvli a2, a0, e8, m1, d1
+# CHECK-ENCODING: [0x57,0x76,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 05 00 <unknown>
+
+th.vsetvli a2, a0, e16, m1, d1
+# CHECK-INST: th.vsetvli a2, a0, e16, m1, d1
+# CHECK-ENCODING: [0x57,0x76,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 45 00 <unknown>
+
+th.vsetvli a2, a0, e32, m1, d1
+# CHECK-INST: th.vsetvli a2, a0, e32, m1, d1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 85 00 <unknown>
+
+th.vsetvli a2, a0, e64, m1, d1
+# CHECK-INST: th.vsetvli a2, a0, e64, m1, d1
+# CHECK-ENCODING: [0x57,0x76,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 c5 00 <unknown>
+
+th.vsetvl a2, a0, a1
+# CHECK-INST: th.vsetvl a2, a0, a1
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 76 b5 80 <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/xor.s b/llvm/test/MC/RISCV/xtheadvector/xor.s
new file mode 100644
index 00000000000000..2d4a839bf80db8
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/xor.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vxor.vv v8, v4, v20, v0.t
+# CHECK-INST: th.vxor.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 2c <unknown>
+
+th.vxor.vv v8, v4, v20
+# CHECK-INST: th.vxor.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a 2e <unknown>
+
+th.vxor.vx v8, v4, a0, v0.t
+# CHECK-INST: th.vxor.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 2c <unknown>
+
+th.vxor.vx v8, v4, a0
+# CHECK-INST: th.vxor.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 2e <unknown>
+
+th.vxor.vi v8, v4, 15, v0.t
+# CHECK-INST: th.vxor.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 2c <unknown>
+
+th.vxor.vi v8, v4, 15
+# CHECK-INST: th.vxor.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 b4 47 2e <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/zvlsseg.s b/llvm/test/MC/RISCV/xtheadvector/zvlsseg.s
new file mode 100644
index 00000000000000..e5daf727bb316b
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/zvlsseg.s
@@ -0,0 +1,3370 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --riscv-no-aliases \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector -M no-aliases - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vlseg2b.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 30 <unknown>
+
+th.vlseg2b.v v8, (a0)
+# CHECK-INST: th.vlseg2b.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 32 <unknown>
+
+th.vlseg2h.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 30 <unknown>
+
+th.vlseg2h.v v8, (a0)
+# CHECK-INST: th.vlseg2h.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 32 <unknown>
+
+th.vlseg2w.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 30 <unknown>
+
+th.vlseg2w.v v8, (a0)
+# CHECK-INST: th.vlseg2w.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 32 <unknown>
+
+th.vlseg2bu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2bu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 20 <unknown>
+
+th.vlseg2bu.v v8, (a0)
+# CHECK-INST: th.vlseg2bu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 22 <unknown>
+
+th.vlseg2hu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2hu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 20 <unknown>
+
+th.vlseg2hu.v v8, (a0)
+# CHECK-INST: th.vlseg2hu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 22 <unknown>
+
+th.vlseg2wu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2wu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 20 <unknown>
+
+th.vlseg2wu.v v8, (a0)
+# CHECK-INST: th.vlseg2wu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 22 <unknown>
+
+th.vlseg2e.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 20 <unknown>
+
+th.vlseg2e.v v8, (a0)
+# CHECK-INST: th.vlseg2e.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 22 <unknown>
+
+th.vsseg2b.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg2b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 20 <unknown>
+
+th.vsseg2b.v v8, (a0)
+# CHECK-INST: th.vsseg2b.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 22 <unknown>
+
+th.vsseg2h.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg2h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 20 <unknown>
+
+th.vsseg2h.v v8, (a0)
+# CHECK-INST: th.vsseg2h.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 22 <unknown>
+
+th.vsseg2w.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg2w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 20 <unknown>
+
+th.vsseg2w.v v8, (a0)
+# CHECK-INST: th.vsseg2w.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 22 <unknown>
+
+th.vsseg2e.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg2e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 20 <unknown>
+
+th.vsseg2e.v v8, (a0)
+# CHECK-INST: th.vsseg2e.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 22 <unknown>
+
+th.vlseg2bff.v v8, (a0)
+# CHECK-INST: th.vlseg2bff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 33 <unknown>
+
+th.vlseg2bff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2bff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 31 <unknown>
+
+th.vlseg2hff.v v8, (a0)
+# CHECK-INST: th.vlseg2hff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 33 <unknown>
+
+th.vlseg2hff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2hff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 31 <unknown>
+
+th.vlseg2wff.v v8, (a0)
+# CHECK-INST: th.vlseg2wff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 33 <unknown>
+
+th.vlseg2wff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2wff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 31 <unknown>
+
+th.vlseg2buff.v v8, (a0)
+# CHECK-INST: th.vlseg2buff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 23 <unknown>
+
+th.vlseg2buff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2buff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 21 <unknown>
+
+th.vlseg2huff.v v8, (a0)
+# CHECK-INST: th.vlseg2huff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 23 <unknown>
+
+th.vlseg2huff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2huff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 21 <unknown>
+
+th.vlseg2wuff.v v8, (a0)
+# CHECK-INST: th.vlseg2wuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 23 <unknown>
+
+th.vlseg2wuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2wuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 21 <unknown>
+
+th.vlseg2eff.v v8, (a0)
+# CHECK-INST: th.vlseg2eff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 23 <unknown>
+
+th.vlseg2eff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg2eff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 21 <unknown>
+
+th.vlsseg2b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 38 <unknown>
+
+th.vlsseg2b.v v8, (a0), a1
+# CHECK-INST: th.vlsseg2b.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 3a <unknown>
+
+th.vlsseg2h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 38 <unknown>
+
+th.vlsseg2h.v v8, (a0), a1
+# CHECK-INST: th.vlsseg2h.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 3a <unknown>
+
+th.vlsseg2w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 38 <unknown>
+
+th.vlsseg2w.v v8, (a0), a1
+# CHECK-INST: th.vlsseg2w.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 3a <unknown>
+
+th.vlsseg2bu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2bu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 28 <unknown>
+
+th.vlsseg2bu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg2bu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
+
+th.vlsseg2hu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2hu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 28 <unknown>
+
+th.vlsseg2hu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg2hu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 2a <unknown>
+
+th.vlsseg2wu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2wu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 28 <unknown>
+
+th.vlsseg2wu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg2wu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 2a <unknown>
+
+th.vlsseg2e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 28 <unknown>
+
+th.vlsseg2e.v v8, (a0), a1
+# CHECK-INST: th.vlsseg2e.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 2a <unknown>
+
+th.vssseg2b.v v8, (a0), a1
+# CHECK-INST: th.vssseg2b.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 2a <unknown>
+
+th.vssseg2b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 28 <unknown>
+
+th.vssseg2h.v v8, (a0), a1
+# CHECK-INST: th.vssseg2h.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 2a <unknown>
+
+th.vssseg2h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 28 <unknown>
+
+th.vssseg2w.v v8, (a0), a1
+# CHECK-INST: th.vssseg2w.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 2a <unknown>
+
+th.vssseg2w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 28 <unknown>
+
+th.vssseg2e.v v8, (a0), a1
+# CHECK-INST: th.vssseg2e.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 2a <unknown>
+
+th.vssseg2e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 28 <unknown>
+
+th.vlxseg2b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg2b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 3c <unknown>
+
+th.vlxseg2b.v v8, (a0), v4
+# CHECK-INST: th.vlxseg2b.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 3e <unknown>
+
+th.vlxseg2h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg2h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 3c <unknown>
+
+th.vlxseg2h.v v8, (a0), v4
+# CHECK-INST: th.vlxseg2h.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 3e <unknown>
+
+th.vlxseg2w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg2w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 3c <unknown>
+
+th.vlxseg2w.v v8, (a0), v4
+# CHECK-INST: th.vlxseg2w.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 3e <unknown>
+
+th.vlxseg2bu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg2bu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 2c <unknown>
+
+th.vlxseg2bu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg2bu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 2e <unknown>
+
+th.vlxseg2hu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg2hu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 2c <unknown>
+
+th.vlxseg2hu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg2hu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 2e <unknown>
+
+th.vlxseg2wu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg2wu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 2c <unknown>
+
+th.vlxseg2wu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg2wu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 2e <unknown>
+
+th.vlxseg2e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg2e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 2c <unknown>
+
+th.vlxseg2e.v v8, (a0), v4
+# CHECK-INST: th.vlxseg2e.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 2e <unknown>
+
+th.vsxseg2b.v v8, (a0), v4
+# CHECK-INST: th.vsxseg2b.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 2e <unknown>
+
+th.vsxseg2b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg2b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 2c <unknown>
+
+th.vsxseg2h.v v8, (a0), v4
+# CHECK-INST: th.vsxseg2h.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 2e <unknown>
+
+th.vsxseg2h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg2h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 2c <unknown>
+
+th.vsxseg2w.v v8, (a0), v4
+# CHECK-INST: th.vsxseg2w.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 2e <unknown>
+
+th.vsxseg2w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg2w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 2c <unknown>
+
+th.vsxseg2e.v v8, (a0), v4
+# CHECK-INST: th.vsxseg2e.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 2e <unknown>
+
+th.vsxseg2e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg2e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 2c <unknown>
+
+th.vlseg3b.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 50 <unknown>
+
+th.vlseg3b.v v8, (a0)
+# CHECK-INST: th.vlseg3b.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 52 <unknown>
+
+th.vlseg3h.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 50 <unknown>
+
+th.vlseg3h.v v8, (a0)
+# CHECK-INST: th.vlseg3h.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 52 <unknown>
+
+th.vlseg3w.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 50 <unknown>
+
+th.vlseg3w.v v8, (a0)
+# CHECK-INST: th.vlseg3w.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 52 <unknown>
+
+th.vlseg3bu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3bu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 40 <unknown>
+
+th.vlseg3bu.v v8, (a0)
+# CHECK-INST: th.vlseg3bu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 42 <unknown>
+
+th.vlseg3hu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3hu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 40 <unknown>
+
+th.vlseg3hu.v v8, (a0)
+# CHECK-INST: th.vlseg3hu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 42 <unknown>
+
+th.vlseg3wu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3wu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 40 <unknown>
+
+th.vlseg3wu.v v8, (a0)
+# CHECK-INST: th.vlseg3wu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 42 <unknown>
+
+th.vlseg3e.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 40 <unknown>
+
+th.vlseg3e.v v8, (a0)
+# CHECK-INST: th.vlseg3e.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 42 <unknown>
+
+th.vsseg3b.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg3b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 40 <unknown>
+
+th.vsseg3b.v v8, (a0)
+# CHECK-INST: th.vsseg3b.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 42 <unknown>
+
+th.vsseg3h.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg3h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 40 <unknown>
+
+th.vsseg3h.v v8, (a0)
+# CHECK-INST: th.vsseg3h.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 42 <unknown>
+
+th.vsseg3w.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg3w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 40 <unknown>
+
+th.vsseg3w.v v8, (a0)
+# CHECK-INST: th.vsseg3w.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 42 <unknown>
+
+th.vsseg3e.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg3e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 40 <unknown>
+
+th.vsseg3e.v v8, (a0)
+# CHECK-INST: th.vsseg3e.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 42 <unknown>
+
+th.vlseg3bff.v v8, (a0)
+# CHECK-INST: th.vlseg3bff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 53 <unknown>
+
+th.vlseg3bff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3bff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 51 <unknown>
+
+th.vlseg3hff.v v8, (a0)
+# CHECK-INST: th.vlseg3hff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 53 <unknown>
+
+th.vlseg3hff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3hff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 51 <unknown>
+
+th.vlseg3wff.v v8, (a0)
+# CHECK-INST: th.vlseg3wff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 53 <unknown>
+
+th.vlseg3wff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3wff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 51 <unknown>
+
+th.vlseg3buff.v v8, (a0)
+# CHECK-INST: th.vlseg3buff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 43 <unknown>
+
+th.vlseg3buff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3buff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 41 <unknown>
+
+th.vlseg3huff.v v8, (a0)
+# CHECK-INST: th.vlseg3huff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 43 <unknown>
+
+th.vlseg3huff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3huff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 41 <unknown>
+
+th.vlseg3wuff.v v8, (a0)
+# CHECK-INST: th.vlseg3wuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 43 <unknown>
+
+th.vlseg3wuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3wuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 41 <unknown>
+
+th.vlseg3eff.v v8, (a0)
+# CHECK-INST: th.vlseg3eff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 43 <unknown>
+
+th.vlseg3eff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg3eff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 41 <unknown>
+
+th.vlsseg3b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 58 <unknown>
+
+th.vlsseg3b.v v8, (a0), a1
+# CHECK-INST: th.vlsseg3b.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 5a <unknown>
+
+th.vlsseg3h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 58 <unknown>
+
+th.vlsseg3h.v v8, (a0), a1
+# CHECK-INST: th.vlsseg3h.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 5a <unknown>
+
+th.vlsseg3w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 58 <unknown>
+
+th.vlsseg3w.v v8, (a0), a1
+# CHECK-INST: th.vlsseg3w.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 5a <unknown>
+
+th.vlsseg3bu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3bu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 48 <unknown>
+
+th.vlsseg3bu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg3bu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 4a <unknown>
+
+th.vlsseg3hu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3hu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 48 <unknown>
+
+th.vlsseg3hu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg3hu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 4a <unknown>
+
+th.vlsseg3wu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3wu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 48 <unknown>
+
+th.vlsseg3wu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg3wu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 4a <unknown>
+
+th.vlsseg3e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 48 <unknown>
+
+th.vlsseg3e.v v8, (a0), a1
+# CHECK-INST: th.vlsseg3e.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 4a <unknown>
+
+th.vssseg3b.v v8, (a0), a1
+# CHECK-INST: th.vssseg3b.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 4a <unknown>
+
+th.vssseg3b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 48 <unknown>
+
+th.vssseg3h.v v8, (a0), a1
+# CHECK-INST: th.vssseg3h.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 4a <unknown>
+
+th.vssseg3h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 48 <unknown>
+
+th.vssseg3w.v v8, (a0), a1
+# CHECK-INST: th.vssseg3w.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 4a <unknown>
+
+th.vssseg3w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 48 <unknown>
+
+th.vssseg3e.v v8, (a0), a1
+# CHECK-INST: th.vssseg3e.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 4a <unknown>
+
+th.vssseg3e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 48 <unknown>
+
+th.vlxseg3b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg3b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 5c <unknown>
+
+th.vlxseg3b.v v8, (a0), v4
+# CHECK-INST: th.vlxseg3b.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 5e <unknown>
+
+th.vlxseg3h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg3h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 5c <unknown>
+
+th.vlxseg3h.v v8, (a0), v4
+# CHECK-INST: th.vlxseg3h.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 5e <unknown>
+
+th.vlxseg3w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg3w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 5c <unknown>
+
+th.vlxseg3w.v v8, (a0), v4
+# CHECK-INST: th.vlxseg3w.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 5e <unknown>
+
+th.vlxseg3bu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg3bu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 4c <unknown>
+
+th.vlxseg3bu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg3bu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 4e <unknown>
+
+th.vlxseg3hu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg3hu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 4c <unknown>
+
+th.vlxseg3hu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg3hu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 4e <unknown>
+
+th.vlxseg3wu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg3wu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 4c <unknown>
+
+th.vlxseg3wu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg3wu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 4e <unknown>
+
+th.vlxseg3e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg3e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 4c <unknown>
+
+th.vlxseg3e.v v8, (a0), v4
+# CHECK-INST: th.vlxseg3e.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 4e <unknown>
+
+th.vsxseg3b.v v8, (a0), v4
+# CHECK-INST: th.vsxseg3b.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 4e <unknown>
+
+th.vsxseg3b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg3b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 4c <unknown>
+
+th.vsxseg3h.v v8, (a0), v4
+# CHECK-INST: th.vsxseg3h.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 4e <unknown>
+
+th.vsxseg3h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg3h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 4c <unknown>
+
+th.vsxseg3w.v v8, (a0), v4
+# CHECK-INST: th.vsxseg3w.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 4e <unknown>
+
+th.vsxseg3w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg3w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 4c <unknown>
+
+th.vsxseg3e.v v8, (a0), v4
+# CHECK-INST: th.vsxseg3e.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 4e <unknown>
+
+th.vsxseg3e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg3e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 4c <unknown>
+
+th.vlseg4b.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 70 <unknown>
+
+th.vlseg4b.v v8, (a0)
+# CHECK-INST: th.vlseg4b.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 72 <unknown>
+
+th.vlseg4h.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 70 <unknown>
+
+th.vlseg4h.v v8, (a0)
+# CHECK-INST: th.vlseg4h.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 72 <unknown>
+
+th.vlseg4w.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 70 <unknown>
+
+th.vlseg4w.v v8, (a0)
+# CHECK-INST: th.vlseg4w.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 72 <unknown>
+
+th.vlseg4bu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4bu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 60 <unknown>
+
+th.vlseg4bu.v v8, (a0)
+# CHECK-INST: th.vlseg4bu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 62 <unknown>
+
+th.vlseg4hu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4hu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 60 <unknown>
+
+th.vlseg4hu.v v8, (a0)
+# CHECK-INST: th.vlseg4hu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 62 <unknown>
+
+th.vlseg4wu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4wu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 60 <unknown>
+
+th.vlseg4wu.v v8, (a0)
+# CHECK-INST: th.vlseg4wu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 62 <unknown>
+
+th.vlseg4e.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 60 <unknown>
+
+th.vlseg4e.v v8, (a0)
+# CHECK-INST: th.vlseg4e.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 62 <unknown>
+
+th.vsseg4b.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg4b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 60 <unknown>
+
+th.vsseg4b.v v8, (a0)
+# CHECK-INST: th.vsseg4b.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 62 <unknown>
+
+th.vsseg4h.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg4h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 60 <unknown>
+
+th.vsseg4h.v v8, (a0)
+# CHECK-INST: th.vsseg4h.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 62 <unknown>
+
+th.vsseg4w.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg4w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 60 <unknown>
+
+th.vsseg4w.v v8, (a0)
+# CHECK-INST: th.vsseg4w.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 62 <unknown>
+
+th.vsseg4e.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg4e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 60 <unknown>
+
+th.vsseg4e.v v8, (a0)
+# CHECK-INST: th.vsseg4e.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 62 <unknown>
+
+th.vlseg4bff.v v8, (a0)
+# CHECK-INST: th.vlseg4bff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 73 <unknown>
+
+th.vlseg4bff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4bff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 71 <unknown>
+
+th.vlseg4hff.v v8, (a0)
+# CHECK-INST: th.vlseg4hff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 73 <unknown>
+
+th.vlseg4hff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4hff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 71 <unknown>
+
+th.vlseg4wff.v v8, (a0)
+# CHECK-INST: th.vlseg4wff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 73 <unknown>
+
+th.vlseg4wff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4wff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 71 <unknown>
+
+th.vlseg4buff.v v8, (a0)
+# CHECK-INST: th.vlseg4buff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 63 <unknown>
+
+th.vlseg4buff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4buff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 61 <unknown>
+
+th.vlseg4huff.v v8, (a0)
+# CHECK-INST: th.vlseg4huff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 63 <unknown>
+
+th.vlseg4huff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4huff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 61 <unknown>
+
+th.vlseg4wuff.v v8, (a0)
+# CHECK-INST: th.vlseg4wuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 63 <unknown>
+
+th.vlseg4wuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4wuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 61 <unknown>
+
+th.vlseg4eff.v v8, (a0)
+# CHECK-INST: th.vlseg4eff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 63 <unknown>
+
+th.vlseg4eff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg4eff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 61 <unknown>
+
+th.vlsseg4b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 78 <unknown>
+
+th.vlsseg4b.v v8, (a0), a1
+# CHECK-INST: th.vlsseg4b.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 7a <unknown>
+
+th.vlsseg4h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 78 <unknown>
+
+th.vlsseg4h.v v8, (a0), a1
+# CHECK-INST: th.vlsseg4h.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 7a <unknown>
+
+th.vlsseg4w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 78 <unknown>
+
+th.vlsseg4w.v v8, (a0), a1
+# CHECK-INST: th.vlsseg4w.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 7a <unknown>
+
+th.vlsseg4bu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4bu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 68 <unknown>
+
+th.vlsseg4bu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg4bu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 6a <unknown>
+
+th.vlsseg4hu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4hu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 68 <unknown>
+
+th.vlsseg4hu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg4hu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 6a <unknown>
+
+th.vlsseg4wu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4wu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 68 <unknown>
+
+th.vlsseg4wu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg4wu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 6a <unknown>
+
+th.vlsseg4e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 68 <unknown>
+
+th.vlsseg4e.v v8, (a0), a1
+# CHECK-INST: th.vlsseg4e.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 6a <unknown>
+
+th.vssseg4b.v v8, (a0), a1
+# CHECK-INST: th.vssseg4b.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 6a <unknown>
+
+th.vssseg4b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 68 <unknown>
+
+th.vssseg4h.v v8, (a0), a1
+# CHECK-INST: th.vssseg4h.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 6a <unknown>
+
+th.vssseg4h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 68 <unknown>
+
+th.vssseg4w.v v8, (a0), a1
+# CHECK-INST: th.vssseg4w.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 6a <unknown>
+
+th.vssseg4w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 68 <unknown>
+
+th.vssseg4e.v v8, (a0), a1
+# CHECK-INST: th.vssseg4e.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 6a <unknown>
+
+th.vssseg4e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 68 <unknown>
+
+th.vlxseg4b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg4b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 7c <unknown>
+
+th.vlxseg4b.v v8, (a0), v4
+# CHECK-INST: th.vlxseg4b.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 7e <unknown>
+
+th.vlxseg4h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg4h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 7c <unknown>
+
+th.vlxseg4h.v v8, (a0), v4
+# CHECK-INST: th.vlxseg4h.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 7e <unknown>
+
+th.vlxseg4w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg4w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 7c <unknown>
+
+th.vlxseg4w.v v8, (a0), v4
+# CHECK-INST: th.vlxseg4w.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 7e <unknown>
+
+th.vlxseg4bu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg4bu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 6c <unknown>
+
+th.vlxseg4bu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg4bu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 6e <unknown>
+
+th.vlxseg4hu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg4hu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 6c <unknown>
+
+th.vlxseg4hu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg4hu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 6e <unknown>
+
+th.vlxseg4wu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg4wu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 6c <unknown>
+
+th.vlxseg4wu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg4wu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 6e <unknown>
+
+th.vlxseg4e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg4e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 6c <unknown>
+
+th.vlxseg4e.v v8, (a0), v4
+# CHECK-INST: th.vlxseg4e.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 6e <unknown>
+
+th.vsxseg4b.v v8, (a0), v4
+# CHECK-INST: th.vsxseg4b.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 6e <unknown>
+
+th.vsxseg4b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg4b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 6c <unknown>
+
+th.vsxseg4h.v v8, (a0), v4
+# CHECK-INST: th.vsxseg4h.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 6e <unknown>
+
+th.vsxseg4h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg4h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 6c <unknown>
+
+th.vsxseg4w.v v8, (a0), v4
+# CHECK-INST: th.vsxseg4w.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 6e <unknown>
+
+th.vsxseg4w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg4w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 6c <unknown>
+
+th.vsxseg4e.v v8, (a0), v4
+# CHECK-INST: th.vsxseg4e.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 6e <unknown>
+
+th.vsxseg4e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg4e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 6c <unknown>
+
+th.vlseg5b.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 90 <unknown>
+
+th.vlseg5b.v v8, (a0)
+# CHECK-INST: th.vlseg5b.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 92 <unknown>
+
+th.vlseg5h.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 90 <unknown>
+
+th.vlseg5h.v v8, (a0)
+# CHECK-INST: th.vlseg5h.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 92 <unknown>
+
+th.vlseg5w.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 90 <unknown>
+
+th.vlseg5w.v v8, (a0)
+# CHECK-INST: th.vlseg5w.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 92 <unknown>
+
+th.vlseg5bu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5bu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 80 <unknown>
+
+th.vlseg5bu.v v8, (a0)
+# CHECK-INST: th.vlseg5bu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 82 <unknown>
+
+th.vlseg5hu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5hu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 80 <unknown>
+
+th.vlseg5hu.v v8, (a0)
+# CHECK-INST: th.vlseg5hu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 82 <unknown>
+
+th.vlseg5wu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5wu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 80 <unknown>
+
+th.vlseg5wu.v v8, (a0)
+# CHECK-INST: th.vlseg5wu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 82 <unknown>
+
+th.vlseg5e.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 80 <unknown>
+
+th.vlseg5e.v v8, (a0)
+# CHECK-INST: th.vlseg5e.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 82 <unknown>
+
+th.vsseg5b.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg5b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 80 <unknown>
+
+th.vsseg5b.v v8, (a0)
+# CHECK-INST: th.vsseg5b.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 82 <unknown>
+
+th.vsseg5h.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg5h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 80 <unknown>
+
+th.vsseg5h.v v8, (a0)
+# CHECK-INST: th.vsseg5h.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 82 <unknown>
+
+th.vsseg5w.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg5w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 80 <unknown>
+
+th.vsseg5w.v v8, (a0)
+# CHECK-INST: th.vsseg5w.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 82 <unknown>
+
+th.vsseg5e.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg5e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 80 <unknown>
+
+th.vsseg5e.v v8, (a0)
+# CHECK-INST: th.vsseg5e.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 82 <unknown>
+
+th.vlseg5bff.v v8, (a0)
+# CHECK-INST: th.vlseg5bff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 93 <unknown>
+
+th.vlseg5bff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5bff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 91 <unknown>
+
+th.vlseg5hff.v v8, (a0)
+# CHECK-INST: th.vlseg5hff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 93 <unknown>
+
+th.vlseg5hff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5hff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 91 <unknown>
+
+th.vlseg5wff.v v8, (a0)
+# CHECK-INST: th.vlseg5wff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 93 <unknown>
+
+th.vlseg5wff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5wff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 91 <unknown>
+
+th.vlseg5buff.v v8, (a0)
+# CHECK-INST: th.vlseg5buff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 83 <unknown>
+
+th.vlseg5buff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5buff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 81 <unknown>
+
+th.vlseg5huff.v v8, (a0)
+# CHECK-INST: th.vlseg5huff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 83 <unknown>
+
+th.vlseg5huff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5huff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 81 <unknown>
+
+th.vlseg5wuff.v v8, (a0)
+# CHECK-INST: th.vlseg5wuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 83 <unknown>
+
+th.vlseg5wuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5wuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 81 <unknown>
+
+th.vlseg5eff.v v8, (a0)
+# CHECK-INST: th.vlseg5eff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 83 <unknown>
+
+th.vlseg5eff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg5eff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 81 <unknown>
+
+th.vlsseg5b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 98 <unknown>
+
+th.vlsseg5b.v v8, (a0), a1
+# CHECK-INST: th.vlsseg5b.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 9a <unknown>
+
+th.vlsseg5h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 98 <unknown>
+
+th.vlsseg5h.v v8, (a0), a1
+# CHECK-INST: th.vlsseg5h.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 9a <unknown>
+
+th.vlsseg5w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 98 <unknown>
+
+th.vlsseg5w.v v8, (a0), a1
+# CHECK-INST: th.vlsseg5w.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 9a <unknown>
+
+th.vlsseg5bu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5bu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 88 <unknown>
+
+th.vlsseg5bu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg5bu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 8a <unknown>
+
+th.vlsseg5hu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5hu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 88 <unknown>
+
+th.vlsseg5hu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg5hu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 8a <unknown>
+
+th.vlsseg5wu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5wu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 88 <unknown>
+
+th.vlsseg5wu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg5wu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 8a <unknown>
+
+th.vlsseg5e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 88 <unknown>
+
+th.vlsseg5e.v v8, (a0), a1
+# CHECK-INST: th.vlsseg5e.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 8a <unknown>
+
+th.vssseg5b.v v8, (a0), a1
+# CHECK-INST: th.vssseg5b.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 8a <unknown>
+
+th.vssseg5b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 88 <unknown>
+
+th.vssseg5h.v v8, (a0), a1
+# CHECK-INST: th.vssseg5h.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 8a <unknown>
+
+th.vssseg5h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 88 <unknown>
+
+th.vssseg5w.v v8, (a0), a1
+# CHECK-INST: th.vssseg5w.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 8a <unknown>
+
+th.vssseg5w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 88 <unknown>
+
+th.vssseg5e.v v8, (a0), a1
+# CHECK-INST: th.vssseg5e.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 8a <unknown>
+
+th.vssseg5e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 88 <unknown>
+
+th.vlxseg5b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg5b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 9c <unknown>
+
+th.vlxseg5b.v v8, (a0), v4
+# CHECK-INST: th.vlxseg5b.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 9e <unknown>
+
+th.vlxseg5h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg5h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 9c <unknown>
+
+th.vlxseg5h.v v8, (a0), v4
+# CHECK-INST: th.vlxseg5h.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 9e <unknown>
+
+th.vlxseg5w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg5w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 9c <unknown>
+
+th.vlxseg5w.v v8, (a0), v4
+# CHECK-INST: th.vlxseg5w.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 9e <unknown>
+
+th.vlxseg5bu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg5bu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 8c <unknown>
+
+th.vlxseg5bu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg5bu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 8e <unknown>
+
+th.vlxseg5hu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg5hu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 8c <unknown>
+
+th.vlxseg5hu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg5hu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 8e <unknown>
+
+th.vlxseg5wu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg5wu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 8c <unknown>
+
+th.vlxseg5wu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg5wu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 8e <unknown>
+
+th.vlxseg5e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg5e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 8c <unknown>
+
+th.vlxseg5e.v v8, (a0), v4
+# CHECK-INST: th.vlxseg5e.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 8e <unknown>
+
+th.vsxseg5b.v v8, (a0), v4
+# CHECK-INST: th.vsxseg5b.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 8e <unknown>
+
+th.vsxseg5b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg5b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 8c <unknown>
+
+th.vsxseg5h.v v8, (a0), v4
+# CHECK-INST: th.vsxseg5h.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 8e <unknown>
+
+th.vsxseg5h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg5h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 8c <unknown>
+
+th.vsxseg5w.v v8, (a0), v4
+# CHECK-INST: th.vsxseg5w.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 8e <unknown>
+
+th.vsxseg5w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg5w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 8c <unknown>
+
+th.vsxseg5e.v v8, (a0), v4
+# CHECK-INST: th.vsxseg5e.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 8e <unknown>
+
+th.vsxseg5e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg5e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 8c <unknown>
+
+th.vlseg6b.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 b0 <unknown>
+
+th.vlseg6b.v v8, (a0)
+# CHECK-INST: th.vlseg6b.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 b2 <unknown>
+
+th.vlseg6h.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 b0 <unknown>
+
+th.vlseg6h.v v8, (a0)
+# CHECK-INST: th.vlseg6h.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 b2 <unknown>
+
+th.vlseg6w.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 b0 <unknown>
+
+th.vlseg6w.v v8, (a0)
+# CHECK-INST: th.vlseg6w.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 b2 <unknown>
+
+th.vlseg6bu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6bu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 a0 <unknown>
+
+th.vlseg6bu.v v8, (a0)
+# CHECK-INST: th.vlseg6bu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 a2 <unknown>
+
+th.vlseg6hu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6hu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 a0 <unknown>
+
+th.vlseg6hu.v v8, (a0)
+# CHECK-INST: th.vlseg6hu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 a2 <unknown>
+
+th.vlseg6wu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6wu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 a0 <unknown>
+
+th.vlseg6wu.v v8, (a0)
+# CHECK-INST: th.vlseg6wu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 a2 <unknown>
+
+th.vlseg6e.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 a0 <unknown>
+
+th.vlseg6e.v v8, (a0)
+# CHECK-INST: th.vlseg6e.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 a2 <unknown>
+
+th.vsseg6b.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg6b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 a0 <unknown>
+
+th.vsseg6b.v v8, (a0)
+# CHECK-INST: th.vsseg6b.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 a2 <unknown>
+
+th.vsseg6h.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg6h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 a0 <unknown>
+
+th.vsseg6h.v v8, (a0)
+# CHECK-INST: th.vsseg6h.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 a2 <unknown>
+
+th.vsseg6w.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg6w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 a0 <unknown>
+
+th.vsseg6w.v v8, (a0)
+# CHECK-INST: th.vsseg6w.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 a2 <unknown>
+
+th.vsseg6e.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg6e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 a0 <unknown>
+
+th.vsseg6e.v v8, (a0)
+# CHECK-INST: th.vsseg6e.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 a2 <unknown>
+
+th.vlseg6bff.v v8, (a0)
+# CHECK-INST: th.vlseg6bff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 b3 <unknown>
+
+th.vlseg6bff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6bff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 b1 <unknown>
+
+th.vlseg6hff.v v8, (a0)
+# CHECK-INST: th.vlseg6hff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 b3 <unknown>
+
+th.vlseg6hff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6hff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 b1 <unknown>
+
+th.vlseg6wff.v v8, (a0)
+# CHECK-INST: th.vlseg6wff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 b3 <unknown>
+
+th.vlseg6wff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6wff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 b1 <unknown>
+
+th.vlseg6buff.v v8, (a0)
+# CHECK-INST: th.vlseg6buff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 a3 <unknown>
+
+th.vlseg6buff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6buff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 a1 <unknown>
+
+th.vlseg6huff.v v8, (a0)
+# CHECK-INST: th.vlseg6huff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 a3 <unknown>
+
+th.vlseg6huff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6huff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 a1 <unknown>
+
+th.vlseg6wuff.v v8, (a0)
+# CHECK-INST: th.vlseg6wuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 a3 <unknown>
+
+th.vlseg6wuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6wuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 a1 <unknown>
+
+th.vlseg6eff.v v8, (a0)
+# CHECK-INST: th.vlseg6eff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 a3 <unknown>
+
+th.vlseg6eff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg6eff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 a1 <unknown>
+
+th.vlsseg6b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 b8 <unknown>
+
+th.vlsseg6b.v v8, (a0), a1
+# CHECK-INST: th.vlsseg6b.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 ba <unknown>
+
+th.vlsseg6h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 b8 <unknown>
+
+th.vlsseg6h.v v8, (a0), a1
+# CHECK-INST: th.vlsseg6h.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 ba <unknown>
+
+th.vlsseg6w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 b8 <unknown>
+
+th.vlsseg6w.v v8, (a0), a1
+# CHECK-INST: th.vlsseg6w.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 ba <unknown>
+
+th.vlsseg6bu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6bu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 a8 <unknown>
+
+th.vlsseg6bu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg6bu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 aa <unknown>
+
+th.vlsseg6hu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6hu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 a8 <unknown>
+
+th.vlsseg6hu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg6hu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 aa <unknown>
+
+th.vlsseg6wu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6wu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 a8 <unknown>
+
+th.vlsseg6wu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg6wu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 aa <unknown>
+
+th.vlsseg6e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 a8 <unknown>
+
+th.vlsseg6e.v v8, (a0), a1
+# CHECK-INST: th.vlsseg6e.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 aa <unknown>
+
+th.vssseg6b.v v8, (a0), a1
+# CHECK-INST: th.vssseg6b.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 aa <unknown>
+
+th.vssseg6b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 a8 <unknown>
+
+th.vssseg6h.v v8, (a0), a1
+# CHECK-INST: th.vssseg6h.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 aa <unknown>
+
+th.vssseg6h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 a8 <unknown>
+
+th.vssseg6w.v v8, (a0), a1
+# CHECK-INST: th.vssseg6w.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 aa <unknown>
+
+th.vssseg6w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 a8 <unknown>
+
+th.vssseg6e.v v8, (a0), a1
+# CHECK-INST: th.vssseg6e.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 aa <unknown>
+
+th.vssseg6e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 a8 <unknown>
+
+th.vlxseg6b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg6b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 bc <unknown>
+
+th.vlxseg6b.v v8, (a0), v4
+# CHECK-INST: th.vlxseg6b.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 be <unknown>
+
+th.vlxseg6h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg6h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 bc <unknown>
+
+th.vlxseg6h.v v8, (a0), v4
+# CHECK-INST: th.vlxseg6h.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 be <unknown>
+
+th.vlxseg6w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg6w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 bc <unknown>
+
+th.vlxseg6w.v v8, (a0), v4
+# CHECK-INST: th.vlxseg6w.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 be <unknown>
+
+th.vlxseg6bu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg6bu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 ac <unknown>
+
+th.vlxseg6bu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg6bu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 ae <unknown>
+
+th.vlxseg6hu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg6hu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 ac <unknown>
+
+th.vlxseg6hu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg6hu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 ae <unknown>
+
+th.vlxseg6wu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg6wu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 ac <unknown>
+
+th.vlxseg6wu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg6wu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 ae <unknown>
+
+th.vlxseg6e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg6e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 ac <unknown>
+
+th.vlxseg6e.v v8, (a0), v4
+# CHECK-INST: th.vlxseg6e.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 ae <unknown>
+
+th.vsxseg6b.v v8, (a0), v4
+# CHECK-INST: th.vsxseg6b.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 ae <unknown>
+
+th.vsxseg6b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg6b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 ac <unknown>
+
+th.vsxseg6h.v v8, (a0), v4
+# CHECK-INST: th.vsxseg6h.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 ae <unknown>
+
+th.vsxseg6h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg6h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 ac <unknown>
+
+th.vsxseg6w.v v8, (a0), v4
+# CHECK-INST: th.vsxseg6w.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 ae <unknown>
+
+th.vsxseg6w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg6w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 ac <unknown>
+
+th.vsxseg6e.v v8, (a0), v4
+# CHECK-INST: th.vsxseg6e.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 ae <unknown>
+
+th.vsxseg6e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg6e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 ac <unknown>
+
+th.vlseg7b.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 d0 <unknown>
+
+th.vlseg7b.v v8, (a0)
+# CHECK-INST: th.vlseg7b.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 d2 <unknown>
+
+th.vlseg7h.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 d0 <unknown>
+
+th.vlseg7h.v v8, (a0)
+# CHECK-INST: th.vlseg7h.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 d2 <unknown>
+
+th.vlseg7w.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 d0 <unknown>
+
+th.vlseg7w.v v8, (a0)
+# CHECK-INST: th.vlseg7w.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 d2 <unknown>
+
+th.vlseg7bu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7bu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 c0 <unknown>
+
+th.vlseg7bu.v v8, (a0)
+# CHECK-INST: th.vlseg7bu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 c2 <unknown>
+
+th.vlseg7hu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7hu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 c0 <unknown>
+
+th.vlseg7hu.v v8, (a0)
+# CHECK-INST: th.vlseg7hu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 c2 <unknown>
+
+th.vlseg7wu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7wu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 c0 <unknown>
+
+th.vlseg7wu.v v8, (a0)
+# CHECK-INST: th.vlseg7wu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 c2 <unknown>
+
+th.vlseg7e.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 c0 <unknown>
+
+th.vlseg7e.v v8, (a0)
+# CHECK-INST: th.vlseg7e.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 c2 <unknown>
+
+th.vsseg7b.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg7b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 c0 <unknown>
+
+th.vsseg7b.v v8, (a0)
+# CHECK-INST: th.vsseg7b.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 c2 <unknown>
+
+th.vsseg7h.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg7h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 c0 <unknown>
+
+th.vsseg7h.v v8, (a0)
+# CHECK-INST: th.vsseg7h.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 c2 <unknown>
+
+th.vsseg7w.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg7w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 c0 <unknown>
+
+th.vsseg7w.v v8, (a0)
+# CHECK-INST: th.vsseg7w.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 c2 <unknown>
+
+th.vsseg7e.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg7e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 c0 <unknown>
+
+th.vsseg7e.v v8, (a0)
+# CHECK-INST: th.vsseg7e.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 c2 <unknown>
+
+th.vlseg7bff.v v8, (a0)
+# CHECK-INST: th.vlseg7bff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 d3 <unknown>
+
+th.vlseg7bff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7bff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 d1 <unknown>
+
+th.vlseg7hff.v v8, (a0)
+# CHECK-INST: th.vlseg7hff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 d3 <unknown>
+
+th.vlseg7hff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7hff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 d1 <unknown>
+
+th.vlseg7wff.v v8, (a0)
+# CHECK-INST: th.vlseg7wff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 d3 <unknown>
+
+th.vlseg7wff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7wff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 d1 <unknown>
+
+th.vlseg7buff.v v8, (a0)
+# CHECK-INST: th.vlseg7buff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 c3 <unknown>
+
+th.vlseg7buff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7buff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 c1 <unknown>
+
+th.vlseg7huff.v v8, (a0)
+# CHECK-INST: th.vlseg7huff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 c3 <unknown>
+
+th.vlseg7huff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7huff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 c1 <unknown>
+
+th.vlseg7wuff.v v8, (a0)
+# CHECK-INST: th.vlseg7wuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 c3 <unknown>
+
+th.vlseg7wuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7wuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 c1 <unknown>
+
+th.vlseg7eff.v v8, (a0)
+# CHECK-INST: th.vlseg7eff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 c3 <unknown>
+
+th.vlseg7eff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg7eff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 c1 <unknown>
+
+th.vlsseg7b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 d8 <unknown>
+
+th.vlsseg7b.v v8, (a0), a1
+# CHECK-INST: th.vlsseg7b.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 da <unknown>
+
+th.vlsseg7h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 d8 <unknown>
+
+th.vlsseg7h.v v8, (a0), a1
+# CHECK-INST: th.vlsseg7h.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 da <unknown>
+
+th.vlsseg7w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 d8 <unknown>
+
+th.vlsseg7w.v v8, (a0), a1
+# CHECK-INST: th.vlsseg7w.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 da <unknown>
+
+th.vlsseg7bu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7bu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 c8 <unknown>
+
+th.vlsseg7bu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg7bu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 ca <unknown>
+
+th.vlsseg7hu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7hu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 c8 <unknown>
+
+th.vlsseg7hu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg7hu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 ca <unknown>
+
+th.vlsseg7wu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7wu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 c8 <unknown>
+
+th.vlsseg7wu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg7wu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 ca <unknown>
+
+th.vlsseg7e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 c8 <unknown>
+
+th.vlsseg7e.v v8, (a0), a1
+# CHECK-INST: th.vlsseg7e.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 ca <unknown>
+
+th.vssseg7b.v v8, (a0), a1
+# CHECK-INST: th.vssseg7b.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 ca <unknown>
+
+th.vssseg7b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 c8 <unknown>
+
+th.vssseg7h.v v8, (a0), a1
+# CHECK-INST: th.vssseg7h.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 ca <unknown>
+
+th.vssseg7h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 c8 <unknown>
+
+th.vssseg7w.v v8, (a0), a1
+# CHECK-INST: th.vssseg7w.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 ca <unknown>
+
+th.vssseg7w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 c8 <unknown>
+
+th.vssseg7e.v v8, (a0), a1
+# CHECK-INST: th.vssseg7e.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 ca <unknown>
+
+th.vssseg7e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 c8 <unknown>
+
+th.vlxseg7b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg7b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 dc <unknown>
+
+th.vlxseg7b.v v8, (a0), v4
+# CHECK-INST: th.vlxseg7b.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 de <unknown>
+
+th.vlxseg7h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg7h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 dc <unknown>
+
+th.vlxseg7h.v v8, (a0), v4
+# CHECK-INST: th.vlxseg7h.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 de <unknown>
+
+th.vlxseg7w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg7w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 dc <unknown>
+
+th.vlxseg7w.v v8, (a0), v4
+# CHECK-INST: th.vlxseg7w.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 de <unknown>
+
+th.vlxseg7bu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg7bu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 cc <unknown>
+
+th.vlxseg7bu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg7bu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 ce <unknown>
+
+th.vlxseg7hu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg7hu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 cc <unknown>
+
+th.vlxseg7hu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg7hu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 ce <unknown>
+
+th.vlxseg7wu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg7wu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 cc <unknown>
+
+th.vlxseg7wu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg7wu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 ce <unknown>
+
+th.vlxseg7e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg7e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 cc <unknown>
+
+th.vlxseg7e.v v8, (a0), v4
+# CHECK-INST: th.vlxseg7e.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 ce <unknown>
+
+th.vsxseg7b.v v8, (a0), v4
+# CHECK-INST: th.vsxseg7b.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 ce <unknown>
+
+th.vsxseg7b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg7b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 cc <unknown>
+
+th.vsxseg7h.v v8, (a0), v4
+# CHECK-INST: th.vsxseg7h.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 ce <unknown>
+
+th.vsxseg7h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg7h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 cc <unknown>
+
+th.vsxseg7w.v v8, (a0), v4
+# CHECK-INST: th.vsxseg7w.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 ce <unknown>
+
+th.vsxseg7w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg7w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 cc <unknown>
+
+th.vsxseg7e.v v8, (a0), v4
+# CHECK-INST: th.vsxseg7e.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 ce <unknown>
+
+th.vsxseg7e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg7e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 cc <unknown>
+
+th.vlseg8b.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 f0 <unknown>
+
+th.vlseg8b.v v8, (a0)
+# CHECK-INST: th.vlseg8b.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 f2 <unknown>
+
+th.vlseg8h.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 f0 <unknown>
+
+th.vlseg8h.v v8, (a0)
+# CHECK-INST: th.vlseg8h.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 f2 <unknown>
+
+th.vlseg8w.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 f0 <unknown>
+
+th.vlseg8w.v v8, (a0)
+# CHECK-INST: th.vlseg8w.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 f2 <unknown>
+
+th.vlseg8bu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8bu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 e0 <unknown>
+
+th.vlseg8bu.v v8, (a0)
+# CHECK-INST: th.vlseg8bu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 e2 <unknown>
+
+th.vlseg8hu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8hu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 e0 <unknown>
+
+th.vlseg8hu.v v8, (a0)
+# CHECK-INST: th.vlseg8hu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 e2 <unknown>
+
+th.vlseg8wu.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8wu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 e0 <unknown>
+
+th.vlseg8wu.v v8, (a0)
+# CHECK-INST: th.vlseg8wu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 e2 <unknown>
+
+th.vlseg8e.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 e0 <unknown>
+
+th.vlseg8e.v v8, (a0)
+# CHECK-INST: th.vlseg8e.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 e2 <unknown>
+
+th.vsseg8b.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg8b.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x04,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 e0 <unknown>
+
+th.vsseg8b.v v8, (a0)
+# CHECK-INST: th.vsseg8b.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x04,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 05 e2 <unknown>
+
+th.vsseg8h.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg8h.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x54,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 e0 <unknown>
+
+th.vsseg8h.v v8, (a0)
+# CHECK-INST: th.vsseg8h.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x54,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 05 e2 <unknown>
+
+th.vsseg8w.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg8w.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x64,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 e0 <unknown>
+
+th.vsseg8w.v v8, (a0)
+# CHECK-INST: th.vsseg8w.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x64,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 05 e2 <unknown>
+
+th.vsseg8e.v v8, (a0), v0.t
+# CHECK-INST: th.vsseg8e.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x74,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 e0 <unknown>
+
+th.vsseg8e.v v8, (a0)
+# CHECK-INST: th.vsseg8e.v v8, (a0)
+# CHECK-ENCODING: [0x27,0x74,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 05 e2 <unknown>
+
+th.vlseg8bff.v v8, (a0)
+# CHECK-INST: th.vlseg8bff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 f3 <unknown>
+
+th.vlseg8bff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8bff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 f1 <unknown>
+
+th.vlseg8hff.v v8, (a0)
+# CHECK-INST: th.vlseg8hff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 f3 <unknown>
+
+th.vlseg8hff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8hff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 f1 <unknown>
+
+th.vlseg8wff.v v8, (a0)
+# CHECK-INST: th.vlseg8wff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 f3 <unknown>
+
+th.vlseg8wff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8wff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 f1 <unknown>
+
+th.vlseg8buff.v v8, (a0)
+# CHECK-INST: th.vlseg8buff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 e3 <unknown>
+
+th.vlseg8buff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8buff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 05 e1 <unknown>
+
+th.vlseg8huff.v v8, (a0)
+# CHECK-INST: th.vlseg8huff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 e3 <unknown>
+
+th.vlseg8huff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8huff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 05 e1 <unknown>
+
+th.vlseg8wuff.v v8, (a0)
+# CHECK-INST: th.vlseg8wuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 e3 <unknown>
+
+th.vlseg8wuff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8wuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 05 e1 <unknown>
+
+th.vlseg8eff.v v8, (a0)
+# CHECK-INST: th.vlseg8eff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 e3 <unknown>
+
+th.vlseg8eff.v v8, (a0), v0.t
+# CHECK-INST: th.vlseg8eff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 05 e1 <unknown>
+
+th.vlsseg8b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 f8 <unknown>
+
+th.vlsseg8b.v v8, (a0), a1
+# CHECK-INST: th.vlsseg8b.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 fa <unknown>
+
+th.vlsseg8h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 f8 <unknown>
+
+th.vlsseg8h.v v8, (a0), a1
+# CHECK-INST: th.vlsseg8h.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 fa <unknown>
+
+th.vlsseg8w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 f8 <unknown>
+
+th.vlsseg8w.v v8, (a0), a1
+# CHECK-INST: th.vlsseg8w.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 fa <unknown>
+
+th.vlsseg8bu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8bu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 e8 <unknown>
+
+th.vlsseg8bu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg8bu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 b5 ea <unknown>
+
+th.vlsseg8hu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8hu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 e8 <unknown>
+
+th.vlsseg8hu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg8hu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 b5 ea <unknown>
+
+th.vlsseg8wu.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8wu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 e8 <unknown>
+
+th.vlsseg8wu.v v8, (a0), a1
+# CHECK-INST: th.vlsseg8wu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 b5 ea <unknown>
+
+th.vlsseg8e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 e8 <unknown>
+
+th.vlsseg8e.v v8, (a0), a1
+# CHECK-INST: th.vlsseg8e.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 b5 ea <unknown>
+
+th.vssseg8b.v v8, (a0), a1
+# CHECK-INST: th.vssseg8b.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x04,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 ea <unknown>
+
+th.vssseg8b.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8b.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x04,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 b5 e8 <unknown>
+
+th.vssseg8h.v v8, (a0), a1
+# CHECK-INST: th.vssseg8h.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x54,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 ea <unknown>
+
+th.vssseg8h.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8h.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x54,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 b5 e8 <unknown>
+
+th.vssseg8w.v v8, (a0), a1
+# CHECK-INST: th.vssseg8w.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x64,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 ea <unknown>
+
+th.vssseg8w.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8w.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x64,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 b5 e8 <unknown>
+
+th.vssseg8e.v v8, (a0), a1
+# CHECK-INST: th.vssseg8e.v v8, (a0), a1
+# CHECK-ENCODING: [0x27,0x74,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 ea <unknown>
+
+th.vssseg8e.v v8, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8e.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x74,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 b5 e8 <unknown>
+
+th.vlxseg8b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg8b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 fc <unknown>
+
+th.vlxseg8b.v v8, (a0), v4
+# CHECK-INST: th.vlxseg8b.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 fe <unknown>
+
+th.vlxseg8h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg8h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 fc <unknown>
+
+th.vlxseg8h.v v8, (a0), v4
+# CHECK-INST: th.vlxseg8h.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 fe <unknown>
+
+th.vlxseg8w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg8w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 fc <unknown>
+
+th.vlxseg8w.v v8, (a0), v4
+# CHECK-INST: th.vlxseg8w.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 fe <unknown>
+
+th.vlxseg8bu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg8bu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 ec <unknown>
+
+th.vlxseg8bu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg8bu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 04 45 ee <unknown>
+
+th.vlxseg8hu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg8hu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 ec <unknown>
+
+th.vlxseg8hu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg8hu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 54 45 ee <unknown>
+
+th.vlxseg8wu.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg8wu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 ec <unknown>
+
+th.vlxseg8wu.v v8, (a0), v4
+# CHECK-INST: th.vlxseg8wu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 64 45 ee <unknown>
+
+th.vlxseg8e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vlxseg8e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 ec <unknown>
+
+th.vlxseg8e.v v8, (a0), v4
+# CHECK-INST: th.vlxseg8e.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 07 74 45 ee <unknown>
+
+th.vsxseg8b.v v8, (a0), v4
+# CHECK-INST: th.vsxseg8b.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x04,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 ee <unknown>
+
+th.vsxseg8b.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg8b.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x04,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 04 45 ec <unknown>
+
+th.vsxseg8h.v v8, (a0), v4
+# CHECK-INST: th.vsxseg8h.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x54,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 ee <unknown>
+
+th.vsxseg8h.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg8h.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x54,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 54 45 ec <unknown>
+
+th.vsxseg8w.v v8, (a0), v4
+# CHECK-INST: th.vsxseg8w.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x64,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 ee <unknown>
+
+th.vsxseg8w.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg8w.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x64,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 64 45 ec <unknown>
+
+th.vsxseg8e.v v8, (a0), v4
+# CHECK-INST: th.vsxseg8e.v v8, (a0), v4
+# CHECK-ENCODING: [0x27,0x74,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 ee <unknown>
+
+th.vsxseg8e.v v8, (a0), v4, v0.t
+# CHECK-INST: th.vsxseg8e.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x74,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 27 74 45 ec <unknown>
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 82cf4c639b6160..1ae0097b2efc87 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -559,6 +559,12 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"'zcf' is only supported for 'rv32'");
}
+
+ for (StringRef Input : {"rv64iv_xtheadvector", "rv32iv_xtheadvector"}) {
+ EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'xtheadvector' extension is incompatible with "
+ "'v' or 'zve*' extension");
+ }
}
TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) {
>From edb3f7e222dc25b8f1dfba03d522ff84315b4aab Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Mon, 26 Feb 2024 15:53:01 +0800
Subject: [PATCH 2/9] fix LLVM MC and related tests
upstream change: c532ba4edd7ad7675ba450ba43268aa9e7bda46b
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 +-
.../RISCV/Disassembler/RISCVDisassembler.cpp | 2 +-
llvm/lib/Target/RISCV/RISCV.td | 7 -
llvm/lib/Target/RISCV/RISCVFeatures.td | 46 +-
.../lib/Target/RISCV/RISCVInstrInfoXTHeadV.td | 932 +++++++++++-------
llvm/test/MC/RISCV/xtheadvector/add.s | 3 +
llvm/test/MC/RISCV/xtheadvector/and.s | 3 +
llvm/test/MC/RISCV/xtheadvector/clip.s | 3 +
llvm/test/MC/RISCV/xtheadvector/compare.s | 3 +
llvm/test/MC/RISCV/xtheadvector/mv.s | 3 +
llvm/test/MC/RISCV/xtheadvector/or.s | 3 +
llvm/test/MC/RISCV/xtheadvector/others.s | 3 +
llvm/test/MC/RISCV/xtheadvector/shift.s | 3 +
llvm/test/MC/RISCV/xtheadvector/sub.s | 3 +
llvm/test/MC/RISCV/xtheadvector/vsetvl.s | 2 +-
llvm/test/MC/RISCV/xtheadvector/xor.s | 3 +
16 files changed, 627 insertions(+), 397 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 920009ab72baa9..6e39ecea0b770f 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1385,10 +1385,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
bool MatchingInlineAsm) {
MCInst Inst;
FeatureBitset MissingFeatures;
- bool IsRVV0p71 = getSTI().hasFeature(RISCV::FeatureVendorXTHeadV);
auto Result = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
- MatchingInlineAsm, IsRVV0p71 ? 1 : 0);
+ MatchingInlineAsm);
switch (Result) {
default:
break;
@@ -1620,7 +1619,7 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return Error(
ErrorLoc,
"operand must be "
- "e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|8] for RVV0.71");
+ "e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|8] for XTHeadVector");
}
case Match_InvalidVMaskRegister: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index fe636a2bdd2e2f..a1ece2e3e58d4e 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -582,7 +582,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
"XTHeadVdot custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV, DecoderTableRVV0p7132,
- "XTHeadV custom opcode table");
+ "XTHeadVector custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custom opcode table");
TRY_TO_DECODE_FEATURE(
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 6136059215023b..575bd4c9d3561d 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -69,16 +69,9 @@ def RISCVAsmWriter : AsmWriter {
int PassSubtarget = 1;
}
-def RVV0p71AsmParserVariant : AsmParserVariant {
- int Variant = 1;
- string Name = "RVV0p71";
-}
-
def RISCV : Target {
let InstructionSet = RISCVInstrInfo;
let AssemblyParsers = [RISCVAsmParser];
- let AssemblyParserVariants = [DefaultAsmParserVariant,
- RVV0p71AsmParserVariant];
let AssemblyWriters = [RISCVAsmWriter];
let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9b2748cf0748de..11e97007e7186a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1232,40 +1232,26 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+def FeatureForcedSWShadowStack : SubtargetFeature<
+ "forced-sw-shadow-stack", "HasForcedSWShadowStack", "true",
+ "Implement shadow stack with software.">;
+def HasForcedSWShadowStack : Predicate<"Subtarget->hasForcedSWShadowStack()">;
+
//===----------------------------------------------------------------------===//
-// T-Head in RuyiSDK specific features and extensions (mostly rvv 0.7.1)
+// T-Head Vector in RuyiSDK specific features and extensions
//===----------------------------------------------------------------------===//
def FeatureVendorXTHeadV
- : SubtargetFeature<"xtheadv", "HasVendorXTHeadV", "true",
- "'xtheadv' (T-Head Base Vector Instructions)">;
+ : SubtargetFeature<"xtheadvector", "HasVendorXTHeadV", "true",
+ "'xtheadvector' (T-Head Base Vector Instructions)">;
def HasVendorXTHeadV : Predicate<"Subtarget->hasVendorXTHeadV()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadV),
- "'xtheadv' (T-Head Base Vector Instructions)">;
-
-def FeatureVendorXTHeadVlsseg
- : SubtargetFeature<"xtheadvlsseg", "HasVendorXTHeadVlsseg", "true",
- "'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions)">;
-def HasVendorXTHeadVlsseg : Predicate<"Subtarget->hasVendorXTHeadVlsseg()">,
- AssemblerPredicate<(all_of FeatureVendorXTHeadVlsseg),
- "'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions)">;
-
-def FeatureVendorXTHeadVamo
- : SubtargetFeature<"xtheadvamo", "HasVendorXTHeadVamo", "true",
- "'xtheadvamo' (T-Head Vector AMO Operations)",
- [FeatureStdExtA]>;
-def HasVendorXTHeadVamo : Predicate<"Subtarget->hasVendorXTHeadVamo()">,
- AssemblerPredicate<(all_of FeatureVendorXTHeadVamo),
- "'xtheadvamo' (T-Head Vector AMO Operations)">;
+ "'xtheadvector' (T-Head Base Vector Instructions)">;
-def FeatureVendorXTHeadVediv
- : SubtargetFeature<"xtheadvediv", "HasVendorXTHeadVediv", "true",
- "'xtheadvediv' (T-Head Divided Element Extension)">;
-def HasVendorXTHeadVediv : Predicate<"Subtarget->hasVendorXTHeadVediv()">,
- AssemblerPredicate<(all_of FeatureVendorXTHeadVediv),
- "'xtheadvediv' (T-Head Divided Element Extension)">;
-
-def FeatureForcedSWShadowStack : SubtargetFeature<
- "forced-sw-shadow-stack", "HasForcedSWShadowStack", "true",
- "Implement shadow stack with software.">;
-def HasForcedSWShadowStack : Predicate<"Subtarget->hasForcedSWShadowStack()">;
+def FeatureVendorXTHeadZvamo
+ : SubtargetFeature<"xtheadzvamo", "HasVendorXTHeadZvamo", "true",
+ "'xtheadzvamo' (T-Head Vector AMO Operations)",
+ [FeatureStdExtA]>;
+def HasVendorXTHeadZvamo : Predicate<"Subtarget->hasVendorXTHeadZvamo()">,
+ AssemblerPredicate<(all_of FeatureVendorXTHeadZvamo),
+ "'xtheadzvamo' (T-Head Vector AMO Operations)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
index f8e531fd4c598d..f9ed15c61b3cb6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
@@ -40,9 +40,9 @@ def XTHeadVTypeI : Operand<XLenVT> {
// Instruction class templates
//===----------------------------------------------------------------------===//
-class XVLoadStore<bits<3> nf, RISCVOpcode opcode,
- bits<3> mop, bits<3> width, dag outs, dag ins,
- string opcodestr, string argstr>
+class TH_VLoadStore<bits<3> nf, RISCVOpcode opcode,
+ bits<3> mop, bits<3> width, dag outs, dag ins,
+ string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs2;
bits<5> rs1;
@@ -62,70 +62,70 @@ class XVLoadStore<bits<3> nf, RISCVOpcode opcode,
}
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, RVVConstraint = VMConstraint in {
- class XVLxU<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
- opcodestr, "$rd, ${rs1}$vm"> {
+ class TH_VLxU<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
let rs2 = 0b00000;
}
- class XVLx<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
- opcodestr, "$rd, ${rs1}$vm"> {
+ class TH_VLx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
let rs2 = 0b00000;
}
- class XVLxUFF<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
- opcodestr, "$rd, ${rs1}$vm"> {
+ class TH_VLxUFF<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
let rs2 = 0b10000;
}
- class XVLxFF<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
- opcodestr, "$rd, ${rs1}$vm"> {
+ class TH_VLxFF<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
let rs2 = 0b10000;
}
- class XVLSxU<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b010, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
- opcodestr, "$rd, $rs1, $rs2$vm">;
- class XVLSx<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b110, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
- opcodestr, "$rd, $rs1, $rs2$vm">;
- class XVLXxU<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b011, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
- opcodestr, "$rd, $rs1, $rs2$vm">;
- class XVLXx<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_LOAD_FP, 0b111, width, (outs VR:$rd),
- (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
- opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VLSxU<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b010, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VLSx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b110, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VLXxU<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b011, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VLXx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b111, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
- class XVSx<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_STORE_FP, 0b000, width, (outs),
- (ins VR:$rd, GPRMemZeroOffset:$rs1, VMaskOp:$vm),
- opcodestr, "$rd, ${rs1}$vm"> {
+ class TH_VSx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b000, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
let rs2 = 0b00000;
}
- class XVSSx<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_STORE_FP, 0b010, width, (outs),
- (ins VR:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
- opcodestr, "$rd, $rs1, $rs2$vm">;
- class XVSXx<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_STORE_FP, 0b011, width, (outs),
- (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
- opcodestr, "$rd, $rs1, $rs2$vm">;
- class XVSUXx<bits<3> nf, bits<3> width, string opcodestr>
- : XVLoadStore<nf, OPC_STORE_FP, 0b111, width, (outs),
- (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
- opcodestr, "$rd, $rs1, $rs2$vm">;
-}
-
-multiclass VWSMAC_V_X<string opcodestr, bits<6> funct6> {
+ class TH_VSSx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b010, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VSXx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b011, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VSUXx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b111, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+}
+
+multiclass TH_VWSMAC_V_X<string opcodestr, bits<6> funct6> {
def V : VALUrVV<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVIWMulAddV_WorstCase, ReadVIWMulAddV_WorstCase,
ReadVIWMulAddV_WorstCase, ReadVMask]>;
@@ -134,13 +134,13 @@ multiclass VWSMAC_V_X<string opcodestr, bits<6> funct6> {
ReadVIWMulAddX_WorstCase, ReadVMask]>;
}
-multiclass VWSMAC_X<string opcodestr, bits<6> funct6> {
+multiclass TH_VWSMAC_X<string opcodestr, bits<6> funct6> {
def X : VALUrVX<funct6, OPIVX, opcodestr # ".vx">,
Sched<[WriteVIWMulAddX_WorstCase, ReadVIWMulAddV_WorstCase,
ReadVIWMulAddX_WorstCase, ReadVMask]>;
}
-multiclass XVNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
+multiclass TH_VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVNClipV_WorstCase, ReadVNClipV_WorstCase,
ReadVNClipV_WorstCase, ReadVMask]>;
@@ -152,7 +152,7 @@ multiclass XVNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
ReadVMask]>;
}
-multiclass XVNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
+multiclass TH_VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVNShiftV_WorstCase, ReadVNShiftV_WorstCase,
ReadVNShiftV_WorstCase, ReadVMask]>;
@@ -164,130 +164,255 @@ multiclass XVNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
ReadVMask]>;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// rvv 0.7.1 set vm=1 for `op vd, vs2, vs1, v0`
+class TH_VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VR:$vd),
+ (ins VR:$vs2, VR:$vs1, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $vs1, v0"> {
+ let vm = 1;
+}
+
+// rvv 0.7.1 set vm=1 for `op vd, vs2, rs1, v0`
+class TH_VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VR:$vd),
+ (ins VR:$vs2, GPR:$rs1, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $rs1, v0"> {
+ let vm = 1;
+}
+
+// rvv 0.7.1 set vm=1 for `op vd, vs2, imm, v0`
+class TH_VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
+ : RVInstIVI<funct6, (outs VR:$vd),
+ (ins VR:$vs2, optype:$imm, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $imm, v0"> {
+ let vm = 1;
+}
+
+multiclass TH_VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
+ def VM : TH_VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
+ Sched<[WriteVICALUV_WorstCase, ReadVICALUV_WorstCase,
+ ReadVICALUV_WorstCase, ReadVMask]>;
+ def XM : TH_VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
+ Sched<[WriteVICALUX_WorstCase, ReadVICALUV_WorstCase,
+ ReadVICALUX_WorstCase, ReadVMask]>;
+}
+
+multiclass TH_VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
+ : TH_VALUm_IV_V_X<opcodestr, funct6> {
+ def IM : TH_VALUmVI<funct6, opcodestr # ".vim">,
+ Sched<[WriteVICALUI_WorstCase, ReadVICALUV_WorstCase,
+ ReadVMask]>;
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+class TH_InstVAMO<bits<5> amoop, bits<3> width, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> rs1;
+ bit wd;
+ bit vm;
+
+ let Inst{31-27} = amoop;
+ let Inst{26} = wd;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width;
+ let Inst{6-0} = OPC_AMO.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
+// vamo vd, vs2, (rs1), vd, vm
+class TH_VAMOWd<bits<5> amoop, bits<3> width, string opcodestr>
+ : TH_InstVAMO<amoop, width, (outs VR:$vd_wd),
+ (ins VR:$vs2, GPR:$rs1, VR:$vd, VMaskOp:$vm),
+ opcodestr, "$vd_wd, $vs2, (${rs1}), $vd$vm"> {
+ let Constraints = "$vd_wd = $vd";
+ let wd = 1;
+ bits<5> vd;
+ let Inst{11-7} = vd;
+}
+
+// vamo x0, vs2, (rs1), vs3, vm
+class TH_VAMONoWd<bits<5> amoop, bits<3> width, string opcodestr>
+ : TH_InstVAMO<amoop, width, (outs),
+ (ins VR:$vs2, GPR:$rs1, VR:$vs3, VMaskOp:$vm),
+ opcodestr, "x0, $vs2, (${rs1}), $vs3$vm"> {
+ let wd = 0;
+ bits<5> vs3;
+ let Inst{11-7} = vs3;
+}
+
+} // hasSideEffects = 0, mayLoad = 1, mayStore = 1
+
+multiclass TH_VAMO<bits<5> amoop, bits<3> width, string opcodestr> {
+ def _WD_V : TH_VAMOWd<amoop, width, opcodestr>;
+ def _UNWD_V : TH_VAMONoWd<amoop, width, opcodestr>;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
-let AsmVariantName = "RVV0p71", DecoderNamespace = "RVV0p71" in {
+let DecoderNamespace = "RVV0p71" in {
let Predicates = [HasVendorXTHeadV] in {
// Configuration-Setting Instructions
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
-def XVSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, XTHeadVTypeI:$vtypei),
- "vsetvli", "$rd, $rs1, $vtypei">,
- Sched<[WriteVSETVLI, ReadVSETVLI]>;
-def XVSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
- "vsetvl", "$rd, $rs1, $rs2">,
- Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>;
+def TH_VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, XTHeadVTypeI:$vtypei),
+ "th.vsetvli", "$rd, $rs1, $vtypei">,
+ Sched<[WriteVSETVLI, ReadVSETVLI]>;
+def TH_VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+ "th.vsetvl", "$rd, $rs1, $rs2">,
+ Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>;
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
// Vector Unit-Stride Instructions
-def XVLB_V : XVLx<0b000, 0b000, "vlb.v">;
-def XVLH_V : XVLx<0b000, 0b101, "vlh.v">;
-def XVLW_V : XVLx<0b000, 0b110, "vlw.v">;
-def XVLBU_V : XVLxU<0b000, 0b000, "vlbu.v">;
-def XVLHU_V : XVLxU<0b000, 0b101, "vlhu.v">;
-def XVLWU_V : XVLxU<0b000, 0b110, "vlwu.v">;
-def XVLE_V : XVLxU<0b000, 0b111, "vle.v">;
-def XVSB_V : XVSx<0b000, 0b000, "vsb.v">;
-def XVSH_V : XVSx<0b000, 0b101, "vsh.v">;
-def XVSW_V : XVSx<0b000, 0b110, "vsw.v">;
-def XVSE_V : XVSx<0b000, 0b111, "vse.v">;
+def TH_VLB_V : TH_VLx<0b000, 0b000, "th.vlb.v">;
+def TH_VLH_V : TH_VLx<0b000, 0b101, "th.vlh.v">;
+def TH_VLW_V : TH_VLx<0b000, 0b110, "th.vlw.v">;
+def TH_VLBU_V : TH_VLxU<0b000, 0b000, "th.vlbu.v">;
+def TH_VLHU_V : TH_VLxU<0b000, 0b101, "th.vlhu.v">;
+def TH_VLWU_V : TH_VLxU<0b000, 0b110, "th.vlwu.v">;
+def TH_VLE_V : TH_VLxU<0b000, 0b111, "th.vle.v">;
+def TH_VSB_V : TH_VSx<0b000, 0b000, "th.vsb.v">;
+def TH_VSH_V : TH_VSx<0b000, 0b101, "th.vsh.v">;
+def TH_VSW_V : TH_VSx<0b000, 0b110, "th.vsw.v">;
+def TH_VSE_V : TH_VSx<0b000, 0b111, "th.vse.v">;
// Vector Strided Instructions
-def XVLSB_V : XVLSx<0b000, 0b000, "vlsb.v">;
-def XVLSH_V : XVLSx<0b000, 0b101, "vlsh.v">;
-def XVLSW_V : XVLSx<0b000, 0b110, "vlsw.v">;
-def XVLSBU_V : XVLSxU<0b000, 0b000, "vlsbu.v">;
-def XVLSHU_V : XVLSxU<0b000, 0b101, "vlshu.v">;
-def XVLSWU_V : XVLSxU<0b000, 0b110, "vlswu.v">;
-def XVLSE_V : XVLSxU<0b000, 0b111, "vlse.v">;
-def XVSSB_V : XVSSx<0b000, 0b000, "vssb.v">;
-def XVSSH_V : XVSSx<0b000, 0b101, "vssh.v">;
-def XVSSW_V : XVSSx<0b000, 0b110, "vssw.v">;
-def XVSSE_V : XVSSx<0b000, 0b111, "vsse.v">;
+def TH_VLSB_V : TH_VLSx<0b000, 0b000, "th.vlsb.v">;
+def TH_VLSH_V : TH_VLSx<0b000, 0b101, "th.vlsh.v">;
+def TH_VLSW_V : TH_VLSx<0b000, 0b110, "th.vlsw.v">;
+def TH_VLSBU_V : TH_VLSxU<0b000, 0b000, "th.vlsbu.v">;
+def TH_VLSHU_V : TH_VLSxU<0b000, 0b101, "th.vlshu.v">;
+def TH_VLSWU_V : TH_VLSxU<0b000, 0b110, "th.vlswu.v">;
+def TH_VLSE_V : TH_VLSxU<0b000, 0b111, "th.vlse.v">;
+def TH_VSSB_V : TH_VSSx<0b000, 0b000, "th.vssb.v">;
+def TH_VSSH_V : TH_VSSx<0b000, 0b101, "th.vssh.v">;
+def TH_VSSW_V : TH_VSSx<0b000, 0b110, "th.vssw.v">;
+def TH_VSSE_V : TH_VSSx<0b000, 0b111, "th.vsse.v">;
// Vector indexed loads and stores
-def XVLXB_V : XVLXx<0b000, 0b000, "vlxb.v">;
-def XVLXH_V : XVLXx<0b000, 0b101, "vlxh.v">;
-def XVLXW_V : XVLXx<0b000, 0b110, "vlxw.v">;
-def XVLXBU_V : XVLXxU<0b000, 0b000, "vlxbu.v">;
-def XVLXHU_V : XVLXxU<0b000, 0b101, "vlxhu.v">;
-def XVLXWU_V : XVLXxU<0b000, 0b110, "vlxwu.v">;
-def XVLXE_V : XVLXxU<0b000, 0b111, "vlxe.v">;
-def XVSXB_V : XVSXx<0b000, 0b000, "vsxb.v">;
-def XVSXH_V : XVSXx<0b000, 0b101, "vsxh.v">;
-def XVSXW_V : XVSXx<0b000, 0b110, "vsxw.v">;
-def XVSXE_V : XVSXx<0b000, 0b111, "vsxe.v">;
-def XVSUXB_V : XVSUXx<0b000, 0b000, "vsuxb.v">;
-def XVSUXH_V : XVSUXx<0b000, 0b101, "vsuxh.v">;
-def XVSUXW_V : XVSUXx<0b000, 0b110, "vsuxw.v">;
-def XVSUXE_V : XVSUXx<0b000, 0b111, "vsuxe.v">;
+def TH_VLXB_V : TH_VLXx<0b000, 0b000, "th.vlxb.v">;
+def TH_VLXH_V : TH_VLXx<0b000, 0b101, "th.vlxh.v">;
+def TH_VLXW_V : TH_VLXx<0b000, 0b110, "th.vlxw.v">;
+def TH_VLXBU_V : TH_VLXxU<0b000, 0b000, "th.vlxbu.v">;
+def TH_VLXHU_V : TH_VLXxU<0b000, 0b101, "th.vlxhu.v">;
+def TH_VLXWU_V : TH_VLXxU<0b000, 0b110, "th.vlxwu.v">;
+def TH_VLXE_V : TH_VLXxU<0b000, 0b111, "th.vlxe.v">;
+def TH_VSXB_V : TH_VSXx<0b000, 0b000, "th.vsxb.v">;
+def TH_VSXH_V : TH_VSXx<0b000, 0b101, "th.vsxh.v">;
+def TH_VSXW_V : TH_VSXx<0b000, 0b110, "th.vsxw.v">;
+def TH_VSXE_V : TH_VSXx<0b000, 0b111, "th.vsxe.v">;
+def TH_VSUXB_V : TH_VSUXx<0b000, 0b000, "th.vsuxb.v">;
+def TH_VSUXH_V : TH_VSUXx<0b000, 0b101, "th.vsuxh.v">;
+def TH_VSUXW_V : TH_VSUXx<0b000, 0b110, "th.vsuxw.v">;
+def TH_VSUXE_V : TH_VSUXx<0b000, 0b111, "th.vsuxe.v">;
// Unit-stride Fault-Only-First Loads
-def XVLBFF_V : XVLxFF<0b000, 0b000, "vlbff.v">;
-def XVLHFF_V : XVLxFF<0b000, 0b101, "vlhff.v">;
-def XVLWFF_V : XVLxFF<0b000, 0b110, "vlwff.v">;
-def XVLBUFF_V : XVLxUFF<0b000, 0b000, "vlbuff.v">;
-def XVLHUFF_V : XVLxUFF<0b000, 0b101, "vlhuff.v">;
-def XVLWUFF_V : XVLxUFF<0b000, 0b110, "vlwuff.v">;
-def XVLEFF_V : XVLxUFF<0b000, 0b111, "vleff.v">;
+def TH_VLBFF_V : TH_VLxFF<0b000, 0b000, "th.vlbff.v">;
+def TH_VLHFF_V : TH_VLxFF<0b000, 0b101, "th.vlhff.v">;
+def TH_VLWFF_V : TH_VLxFF<0b000, 0b110, "th.vlwff.v">;
+def TH_VLBUFF_V : TH_VLxUFF<0b000, 0b000, "th.vlbuff.v">;
+def TH_VLHUFF_V : TH_VLxUFF<0b000, 0b101, "th.vlhuff.v">;
+def TH_VLWUFF_V : TH_VLxUFF<0b000, 0b110, "th.vlwuff.v">;
+def TH_VLEFF_V : TH_VLxUFF<0b000, 0b111, "th.vleff.v">;
} // Predicates = [HasVendorXTHeadV]
-let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg] in {
+// The extension `Zvlsseg (chapter 7.8)` is not a subextension but a mandatory part of `XTheadVector`.
+let Predicates = [HasVendorXTHeadV] in {
foreach nf=2-8 in {
// Vector Unit-Stride Segment Loads and Stores
- def XVLSEG#nf#B_V : XVLx<!add(nf, -1), 0b000, "vlseg"#nf#"b.v">;
- def XVLSEG#nf#H_V : XVLx<!add(nf, -1), 0b101, "vlseg"#nf#"h.v">;
- def XVLSEG#nf#W_V : XVLx<!add(nf, -1), 0b110, "vlseg"#nf#"w.v">;
- def XVLSEG#nf#BU_V : XVLxU<!add(nf, -1), 0b000, "vlseg"#nf#"bu.v">;
- def XVLSEG#nf#HU_V : XVLxU<!add(nf, -1), 0b101, "vlseg"#nf#"hu.v">;
- def XVLSEG#nf#WU_V : XVLxU<!add(nf, -1), 0b110, "vlseg"#nf#"wu.v">;
- def XVLSEG#nf#E_V : XVLxU<!add(nf, -1), 0b111, "vlseg"#nf#"e.v">;
- def XVSSEG#nf#B_V : XVSx<!add(nf, -1), 0b000, "vsseg"#nf#"b.v">;
- def XVSSEG#nf#H_V : XVSx<!add(nf, -1), 0b101, "vsseg"#nf#"h.v">;
- def XVSSEG#nf#W_V : XVSx<!add(nf, -1), 0b110, "vsseg"#nf#"w.v">;
- def XVSSEG#nf#E_V : XVSx<!add(nf, -1), 0b111, "vsseg"#nf#"e.v">;
- def XVLSEG#nf#BFF_V : XVLxFF<!add(nf, -1), 0b000, "vlseg"#nf#"bff.v">;
- def XVLSEG#nf#HFF_V : XVLxFF<!add(nf, -1), 0b101, "vlseg"#nf#"hff.v">;
- def XVLSEG#nf#WFF_V : XVLxFF<!add(nf, -1), 0b110, "vlseg"#nf#"wff.v">;
- def XVLSEG#nf#BUFF_V : XVLxUFF<!add(nf, -1), 0b000, "vlseg"#nf#"buff.v">;
- def XVLSEG#nf#HUFF_V : XVLxUFF<!add(nf, -1), 0b101, "vlseg"#nf#"huff.v">;
- def XVLSEG#nf#WUFF_V : XVLxUFF<!add(nf, -1), 0b110, "vlseg"#nf#"wuff.v">;
- def XVLSEG#nf#EFF_V : XVLxUFF<!add(nf, -1), 0b111, "vlseg"#nf#"eff.v">;
+ def TH_VLSEG#nf#B_V : TH_VLx<!add(nf, -1), 0b000, "th.vlseg"#nf#"b.v">;
+ def TH_VLSEG#nf#H_V : TH_VLx<!add(nf, -1), 0b101, "th.vlseg"#nf#"h.v">;
+ def TH_VLSEG#nf#W_V : TH_VLx<!add(nf, -1), 0b110, "th.vlseg"#nf#"w.v">;
+ def TH_VLSEG#nf#BU_V : TH_VLxU<!add(nf, -1), 0b000, "th.vlseg"#nf#"bu.v">;
+ def TH_VLSEG#nf#HU_V : TH_VLxU<!add(nf, -1), 0b101, "th.vlseg"#nf#"hu.v">;
+ def TH_VLSEG#nf#WU_V : TH_VLxU<!add(nf, -1), 0b110, "th.vlseg"#nf#"wu.v">;
+ def TH_VLSEG#nf#E_V : TH_VLxU<!add(nf, -1), 0b111, "th.vlseg"#nf#"e.v">;
+ def TH_VSSEG#nf#B_V : TH_VSx<!add(nf, -1), 0b000, "th.vsseg"#nf#"b.v">;
+ def TH_VSSEG#nf#H_V : TH_VSx<!add(nf, -1), 0b101, "th.vsseg"#nf#"h.v">;
+ def TH_VSSEG#nf#W_V : TH_VSx<!add(nf, -1), 0b110, "th.vsseg"#nf#"w.v">;
+ def TH_VSSEG#nf#E_V : TH_VSx<!add(nf, -1), 0b111, "th.vsseg"#nf#"e.v">;
+ def TH_VLSEG#nf#BFF_V : TH_VLxFF<!add(nf, -1), 0b000, "th.vlseg"#nf#"bff.v">;
+ def TH_VLSEG#nf#HFF_V : TH_VLxFF<!add(nf, -1), 0b101, "th.vlseg"#nf#"hff.v">;
+ def TH_VLSEG#nf#WFF_V : TH_VLxFF<!add(nf, -1), 0b110, "th.vlseg"#nf#"wff.v">;
+ def TH_VLSEG#nf#BUFF_V : TH_VLxUFF<!add(nf, -1), 0b000, "th.vlseg"#nf#"buff.v">;
+ def TH_VLSEG#nf#HUFF_V : TH_VLxUFF<!add(nf, -1), 0b101, "th.vlseg"#nf#"huff.v">;
+ def TH_VLSEG#nf#WUFF_V : TH_VLxUFF<!add(nf, -1), 0b110, "th.vlseg"#nf#"wuff.v">;
+ def TH_VLSEG#nf#EFF_V : TH_VLxUFF<!add(nf, -1), 0b111, "th.vlseg"#nf#"eff.v">;
// Vector Strided Segment Loads and Stores
- def XVLSSEG#nf#B_V : XVLSx<!add(nf, -1), 0b000, "vlsseg"#nf#"b.v">;
- def XVLSSEG#nf#H_V : XVLSx<!add(nf, -1), 0b101, "vlsseg"#nf#"h.v">;
- def XVLSSEG#nf#W_V : XVLSx<!add(nf, -1), 0b110, "vlsseg"#nf#"w.v">;
- def XVLSSEG#nf#BU_V : XVLSxU<!add(nf, -1), 0b000, "vlsseg"#nf#"bu.v">;
- def XVLSSEG#nf#HU_V : XVLSxU<!add(nf, -1), 0b101, "vlsseg"#nf#"hu.v">;
- def XVLSSEG#nf#WU_V : XVLSxU<!add(nf, -1), 0b110, "vlsseg"#nf#"wu.v">;
- def XVLSSEG#nf#E_V : XVLSxU<!add(nf, -1), 0b111, "vlsseg"#nf#"e.v">;
- def XVSSSEG#nf#B_V : XVSSx<!add(nf, -1), 0b000, "vssseg"#nf#"b.v">;
- def XVSSSEG#nf#H_V : XVSSx<!add(nf, -1), 0b101, "vssseg"#nf#"h.v">;
- def XVSSSEG#nf#W_V : XVSSx<!add(nf, -1), 0b110, "vssseg"#nf#"w.v">;
- def XVSSSEG#nf#E_V : XVSSx<!add(nf, -1), 0b111, "vssseg"#nf#"e.v">;
+ def TH_VLSSEG#nf#B_V : TH_VLSx<!add(nf, -1), 0b000, "th.vlsseg"#nf#"b.v">;
+ def TH_VLSSEG#nf#H_V : TH_VLSx<!add(nf, -1), 0b101, "th.vlsseg"#nf#"h.v">;
+ def TH_VLSSEG#nf#W_V : TH_VLSx<!add(nf, -1), 0b110, "th.vlsseg"#nf#"w.v">;
+ def TH_VLSSEG#nf#BU_V : TH_VLSxU<!add(nf, -1), 0b000, "th.vlsseg"#nf#"bu.v">;
+ def TH_VLSSEG#nf#HU_V : TH_VLSxU<!add(nf, -1), 0b101, "th.vlsseg"#nf#"hu.v">;
+ def TH_VLSSEG#nf#WU_V : TH_VLSxU<!add(nf, -1), 0b110, "th.vlsseg"#nf#"wu.v">;
+ def TH_VLSSEG#nf#E_V : TH_VLSxU<!add(nf, -1), 0b111, "th.vlsseg"#nf#"e.v">;
+ def TH_VSSSEG#nf#B_V : TH_VSSx<!add(nf, -1), 0b000, "th.vssseg"#nf#"b.v">;
+ def TH_VSSSEG#nf#H_V : TH_VSSx<!add(nf, -1), 0b101, "th.vssseg"#nf#"h.v">;
+ def TH_VSSSEG#nf#W_V : TH_VSSx<!add(nf, -1), 0b110, "th.vssseg"#nf#"w.v">;
+ def TH_VSSSEG#nf#E_V : TH_VSSx<!add(nf, -1), 0b111, "th.vssseg"#nf#"e.v">;
// Vector Indexed Segment Loads and Stores
- def XVLXSEG#nf#B_V : XVLXx<!add(nf, -1), 0b000, "vlxseg"#nf#"b.v">;
- def XVLXSEG#nf#H_V : XVLXx<!add(nf, -1), 0b101, "vlxseg"#nf#"h.v">;
- def XVLXSEG#nf#W_V : XVLXx<!add(nf, -1), 0b110, "vlxseg"#nf#"w.v">;
- def XVLXSEG#nf#BU_V : XVLXxU<!add(nf, -1), 0b000, "vlxseg"#nf#"bu.v">;
- def XVLXSEG#nf#HU_V : XVLXxU<!add(nf, -1), 0b101, "vlxseg"#nf#"hu.v">;
- def XVLXSEG#nf#WU_V : XVLXxU<!add(nf, -1), 0b110, "vlxseg"#nf#"wu.v">;
- def XVLXSEG#nf#E_V : XVLXxU<!add(nf, -1), 0b111, "vlxseg"#nf#"e.v">;
- def XVSXSEG#nf#B_V : XVSXx<!add(nf, -1), 0b000, "vsxseg"#nf#"b.v">;
- def XVSXSEG#nf#H_V : XVSXx<!add(nf, -1), 0b101, "vsxseg"#nf#"h.v">;
- def XVSXSEG#nf#W_V : XVSXx<!add(nf, -1), 0b110, "vsxseg"#nf#"w.v">;
- def XVSXSEG#nf#E_V : XVSXx<!add(nf, -1), 0b111, "vsxseg"#nf#"e.v">;
-}
-} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg]
+ def TH_VLXSEG#nf#B_V : TH_VLXx<!add(nf, -1), 0b000, "th.vlxseg"#nf#"b.v">;
+ def TH_VLXSEG#nf#H_V : TH_VLXx<!add(nf, -1), 0b101, "th.vlxseg"#nf#"h.v">;
+ def TH_VLXSEG#nf#W_V : TH_VLXx<!add(nf, -1), 0b110, "th.vlxseg"#nf#"w.v">;
+ def TH_VLXSEG#nf#BU_V : TH_VLXxU<!add(nf, -1), 0b000, "th.vlxseg"#nf#"bu.v">;
+ def TH_VLXSEG#nf#HU_V : TH_VLXxU<!add(nf, -1), 0b101, "th.vlxseg"#nf#"hu.v">;
+ def TH_VLXSEG#nf#WU_V : TH_VLXxU<!add(nf, -1), 0b110, "th.vlxseg"#nf#"wu.v">;
+ def TH_VLXSEG#nf#E_V : TH_VLXxU<!add(nf, -1), 0b111, "th.vlxseg"#nf#"e.v">;
+ def TH_VSXSEG#nf#B_V : TH_VSXx<!add(nf, -1), 0b000, "th.vsxseg"#nf#"b.v">;
+ def TH_VSXSEG#nf#H_V : TH_VSXx<!add(nf, -1), 0b101, "th.vsxseg"#nf#"h.v">;
+ def TH_VSXSEG#nf#W_V : TH_VSXx<!add(nf, -1), 0b110, "th.vsxseg"#nf#"w.v">;
+ def TH_VSXSEG#nf#E_V : TH_VSXx<!add(nf, -1), 0b111, "th.vsxseg"#nf#"e.v">;
+}
+} // Predicates = [HasVendorXTHeadV]
+
+// The extension `Zvamo` is renamed to `XTheadZvamo`.
+let Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA] in {
+ // Vector AMO Instruction
+ defm TH_VAMOSWAPW : TH_VAMO<0b00001, 0b110, "th.vamoswapw.v">;
+ defm TH_VAMOADDW : TH_VAMO<0b00000, 0b110, "th.vamoaddw.v">;
+ defm TH_VAMOXORW : TH_VAMO<0b00100, 0b110, "th.vamoxorw.v">;
+ defm TH_VAMOANDW : TH_VAMO<0b01100, 0b110, "th.vamoandw.v">;
+ defm TH_VAMOORW : TH_VAMO<0b01000, 0b110, "th.vamoorw.v">;
+ defm TH_VAMOMINW : TH_VAMO<0b10000, 0b110, "th.vamominw.v">;
+ defm TH_VAMOMAXW : TH_VAMO<0b10100, 0b110, "th.vamomaxw.v">;
+ defm TH_VAMOMINUW : TH_VAMO<0b11000, 0b110, "th.vamominuw.v">;
+ defm TH_VAMOMAXUW : TH_VAMO<0b11100, 0b110, "th.vamomaxuw.v">;
+
+ defm TH_VAMOSWAPD : TH_VAMO<0b00001, 0b111, "th.vamoswapd.v">;
+ defm TH_VAMOADDD : TH_VAMO<0b00000, 0b111, "th.vamoaddd.v">;
+ defm TH_VAMOXORD : TH_VAMO<0b00100, 0b111, "th.vamoxord.v">;
+ defm TH_VAMOANDD : TH_VAMO<0b01100, 0b111, "th.vamoandd.v">;
+ defm TH_VAMOORD : TH_VAMO<0b01000, 0b111, "th.vamoord.v">;
+ defm TH_VAMOMIND : TH_VAMO<0b10000, 0b111, "th.vamomind.v">;
+ defm TH_VAMOMAXD : TH_VAMO<0b10100, 0b111, "th.vamomaxd.v">;
+ defm TH_VAMOMINUD : TH_VAMO<0b11000, 0b111, "th.vamominud.v">;
+ defm TH_VAMOMAXUD : TH_VAMO<0b11100, 0b111, "th.vamomaxud.v">;
+
+ defm TH_VAMOSWAPQ : TH_VAMO<0b00001, 0b000, "th.vamoswapq.v">;
+ defm TH_VAMOADDQ : TH_VAMO<0b00000, 0b000, "th.vamoaddq.v">;
+ defm TH_VAMOXORQ : TH_VAMO<0b00100, 0b000, "th.vamoxorq.v">;
+ defm TH_VAMOANDQ : TH_VAMO<0b01100, 0b000, "th.vamoandq.v">;
+ defm TH_VAMOORQ : TH_VAMO<0b01000, 0b000, "th.vamoorq.v">;
+ defm TH_VAMOMINQ : TH_VAMO<0b10000, 0b000, "th.vamominq.v">;
+ defm TH_VAMOMAXQ : TH_VAMO<0b10100, 0b000, "th.vamomaxq.v">;
+ defm TH_VAMOMINUQ : TH_VAMO<0b11000, 0b000, "th.vamominuq.v">;
+ defm TH_VAMOMAXUQ : TH_VAMO<0b11100, 0b000, "th.vamomaxuq.v">;
+} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA]
let Predicates = [HasVendorXTHeadV] in {
// Vector Single-Width Integer Add and Subtract
-defm XVADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
-defm XVSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
-defm XVRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
+defm TH_VADD_V : VALU_IV_V_X_I<"th.vadd", 0b000000>;
+defm TH_VSUB_V : VALU_IV_V_X<"th.vsub", 0b000010>;
+defm TH_VRSUB_V : VALU_IV_X_I<"th.vrsub", 0b000011>;
// Vector Widening Integer Add/Subtract
// Refer to 11.2 Widening Vector Arithmetic Instructions
@@ -296,44 +421,42 @@ defm XVRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
// if masked), otherwise an illegal instruction exception is raised.
let Constraints = "@earlyclobber $vd" in {
let RVVConstraint = WidenV in {
-defm XVWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000, "v">;
-defm XVWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010, "v">;
-defm XVWADD_V : VALU_MV_V_X<"vwadd", 0b110001, "v">;
-defm XVWSUB_V : VALU_MV_V_X<"vwsub", 0b110011, "v">;
+defm TH_VWADDU_V : VALU_MV_V_X<"th.vwaddu", 0b110000, "v">;
+defm TH_VWSUBU_V : VALU_MV_V_X<"th.vwsubu", 0b110010, "v">;
+defm TH_VWADD_V : VALU_MV_V_X<"th.vwadd", 0b110001, "v">;
+defm TH_VWSUB_V : VALU_MV_V_X<"th.vwsub", 0b110011, "v">;
} // RVVConstraint = WidenV
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
let RVVConstraint = WidenW in {
-defm XVWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">;
-defm XVWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">;
-defm XVWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">;
-defm XVWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
+defm TH_VWADDU_W : VALU_MV_V_X<"th.vwaddu", 0b110100, "w">;
+defm TH_VWSUBU_W : VALU_MV_V_X<"th.vwsubu", 0b110110, "w">;
+defm TH_VWADD_W : VALU_MV_V_X<"th.vwadd", 0b110101, "w">;
+defm TH_VWSUB_W : VALU_MV_V_X<"th.vwsub", 0b110111, "w">;
} // RVVConstraint = WidenW
} // Constraints = "@earlyclobber $vd"
// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
-defm XVADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
+defm TH_VADC_V : TH_VALUm_IV_V_X_I<"th.vadc", 0b010000>;
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
-defm XVMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
-defm XVMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
+defm TH_VMADC_V : TH_VALUm_IV_V_X_I<"th.vmadc", 0b010001>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
-defm XVSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
+defm TH_VSBC_V : TH_VALUm_IV_V_X<"th.vsbc", 0b010010>;
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
-defm XVMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
-defm XVMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
+defm TH_VMSBC_V : TH_VALUm_IV_V_X<"th.vmsbc", 0b010011>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
// Vector Bitwise Logical Instructions
-defm XVAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
-defm XVOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
-defm XVXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
+defm TH_VAND_V : VALU_IV_V_X_I<"th.vand", 0b001001>;
+defm TH_VOR_V : VALU_IV_V_X_I<"th.vor", 0b001010>;
+defm TH_VXOR_V : VALU_IV_V_X_I<"th.vxor", 0b001011>;
// Vector Single-Width Bit Shift Instructions
-defm XVSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101>;
-defm XVSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000>;
-defm XVSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001>;
+defm TH_VSLL_V : VSHT_IV_V_X_I<"th.vsll", 0b100101>;
+defm TH_VSRL_V : VSHT_IV_V_X_I<"th.vsrl", 0b101000>;
+defm TH_VSRA_V : VSHT_IV_V_X_I<"th.vsra", 0b101001>;
// Vector Narrowing Integer Right Shift Instructions
// Refer to 11.3. Narrowing Vector Arithmetic Instructions
@@ -341,119 +464,119 @@ defm XVSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001>;
// vector register group (specified by vs2). The destination vector register
// group cannot overlap the mask register if used, unless LMUL=1.
let Constraints = "@earlyclobber $vd" in {
-defm XVNSRL_W : XVNSHT_IV_V_X_I<"vnsrl", 0b101100>;
-defm XVNSRA_W : XVNSHT_IV_V_X_I<"vnsra", 0b101101>;
+defm TH_VNSRL_W : TH_VNSHT_IV_V_X_I<"th.vnsrl", 0b101100>;
+defm TH_VNSRA_W : TH_VNSHT_IV_V_X_I<"th.vnsra", 0b101101>;
} // Constraints = "@earlyclobber $vd"
// Vector Integer Comparison Instructions
let RVVConstraint = NoConstraint in {
-defm XVMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>;
-defm XVMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>;
-defm XVMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>;
-defm XVMSLT_V : VCMP_IV_V_X<"vmslt", 0b011011>;
-defm XVMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>;
-defm XVMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>;
-defm XVMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>;
-defm XVMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>;
+defm TH_VMSEQ_V : VCMP_IV_V_X_I<"th.vmseq", 0b011000>;
+defm TH_VMSNE_V : VCMP_IV_V_X_I<"th.vmsne", 0b011001>;
+defm TH_VMSLTU_V : VCMP_IV_V_X<"th.vmsltu", 0b011010>;
+defm TH_VMSLT_V : VCMP_IV_V_X<"th.vmslt", 0b011011>;
+defm TH_VMSLEU_V : VCMP_IV_V_X_I<"th.vmsleu", 0b011100>;
+defm TH_VMSLE_V : VCMP_IV_V_X_I<"th.vmsle", 0b011101>;
+defm TH_VMSGTU_V : VCMP_IV_X_I<"th.vmsgtu", 0b011110>;
+defm TH_VMSGT_V : VCMP_IV_X_I<"th.vmsgt", 0b011111>;
} // RVVConstraint = NoConstraint
// Vector Integer Min/Max Instructions
-defm XVMINU_V : VCMP_IV_V_X<"vminu", 0b000100>;
-defm XVMIN_V : VCMP_IV_V_X<"vmin", 0b000101>;
-defm XVMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>;
-defm XVMAX_V : VCMP_IV_V_X<"vmax", 0b000111>;
+defm TH_VMINU_V : VCMP_IV_V_X<"th.vminu", 0b000100>;
+defm TH_VMIN_V : VCMP_IV_V_X<"th.vmin", 0b000101>;
+defm TH_VMAXU_V : VCMP_IV_V_X<"th.vmaxu", 0b000110>;
+defm TH_VMAX_V : VCMP_IV_V_X<"th.vmax", 0b000111>;
// Vector Single-Width Integer Multiply Instructions
-defm XVMUL_V : VMUL_MV_V_X<"vmul", 0b100101>;
-defm XVMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>;
-defm XVMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>;
-defm XVMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>;
+defm TH_VMUL_V : VMUL_MV_V_X<"th.vmul", 0b100101>;
+defm TH_VMULH_V : VMUL_MV_V_X<"th.vmulh", 0b100111>;
+defm TH_VMULHU_V : VMUL_MV_V_X<"th.vmulhu", 0b100100>;
+defm TH_VMULHSU_V : VMUL_MV_V_X<"th.vmulhsu", 0b100110>;
// Vector Integer Divide Instructions
-defm XVDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>;
-defm XVDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>;
-defm XVREMU_V : VDIV_MV_V_X<"vremu", 0b100010>;
-defm XVREM_V : VDIV_MV_V_X<"vrem", 0b100011>;
+defm TH_VDIVU_V : VDIV_MV_V_X<"th.vdivu", 0b100000>;
+defm TH_VDIV_V : VDIV_MV_V_X<"th.vdiv", 0b100001>;
+defm TH_VREMU_V : VDIV_MV_V_X<"th.vremu", 0b100010>;
+defm TH_VREM_V : VDIV_MV_V_X<"th.vrem", 0b100011>;
// Vector Widening Integer Multiply Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
-defm XVWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>;
-defm XVWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>;
-defm XVWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>;
+defm TH_VWMUL_V : VWMUL_MV_V_X<"th.vwmul", 0b111011>;
+defm TH_VWMULU_V : VWMUL_MV_V_X<"th.vwmulu", 0b111000>;
+defm TH_VWMULSU_V : VWMUL_MV_V_X<"th.vwmulsu", 0b111010>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
// Vector Single-Width Integer Multiply-Add Instructions
-defm XVMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>;
-defm XVNMSAC_V : VMAC_MV_V_X<"vnmsac", 0b101111>;
-defm XVMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>;
-defm XVNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>;
+defm TH_VMACC_V : VMAC_MV_V_X<"th.vmacc", 0b101101>;
+defm TH_VNMSAC_V : VMAC_MV_V_X<"th.vnmsac", 0b101111>;
+defm TH_VMADD_V : VMAC_MV_V_X<"th.vmadd", 0b101001>;
+defm TH_VNMSUB_V : VMAC_MV_V_X<"th.vnmsub", 0b101011>;
// Vector Widening Integer Multiply-Add Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
-defm XVWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>;
-defm XVWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>;
-defm XVWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>;
-defm XVWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>;
+defm TH_VWMACCU_V : VWMAC_MV_V_X<"th.vwmaccu", 0b111100>;
+defm TH_VWMACC_V : VWMAC_MV_V_X<"th.vwmacc", 0b111101>;
+defm TH_VWMACCSU_V : VWMAC_MV_V_X<"th.vwmaccsu", 0b111110>;
+defm TH_VWMACCUS_V : VWMAC_MV_X<"th.vwmaccus", 0b111111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
// Vector Integer Merge Instructions
-defm XVMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>;
+defm TH_VMERGE_V : VMRG_IV_V_X_I<"th.vmerge", 0b010111>;
// Vector Integer Move Instructions
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1,
RVVConstraint = NoConstraint in {
// op vd, vs1
-def XVMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd),
- (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">,
- Sched<[WriteVIMovV_WorstCase, ReadVIMovV_WorstCase]>;
+def TH_VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd),
+ (ins VR:$vs1), "th.vmv.v.v", "$vd, $vs1">,
+ Sched<[WriteVIMovV_WorstCase, ReadVIMovV_WorstCase]>;
// op vd, rs1
-def XVMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd),
- (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">,
- Sched<[WriteVIMovX_WorstCase, ReadVIMovX_WorstCase]>;
+def TH_VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd),
+ (ins GPR:$rs1), "th.vmv.v.x", "$vd, $rs1">,
+ Sched<[WriteVIMovX_WorstCase, ReadVIMovX_WorstCase]>;
// op vd, imm
-def XVMV_V_I : RVInstIVI<0b010111, (outs VR:$vd),
- (ins simm5:$imm), "vmv.v.i", "$vd, $imm">,
- Sched<[WriteVIMovI_WorstCase]>;
+def TH_VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd),
+ (ins simm5:$imm), "th.vmv.v.i", "$vd, $imm">,
+ Sched<[WriteVIMovI_WorstCase]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
// Vector Fixed-Point Arithmetic Instructions
-defm XVSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>;
-defm XVSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>;
-defm XVSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>;
-defm XVSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>;
+defm TH_VSADDU_V : VSALU_IV_V_X_I<"th.vsaddu", 0b100000>;
+defm TH_VSADD_V : VSALU_IV_V_X_I<"th.vsadd", 0b100001>;
+defm TH_VSSUBU_V : VSALU_IV_V_X<"th.vssubu", 0b100010>;
+defm TH_VSSUB_V : VSALU_IV_V_X<"th.vssub", 0b100011>;
// Vector Single-Width Averaging Add and Subtract
-defm XVAADD_V : VSALU_IV_V_X_I<"vaadd", 0b100100>;
-defm XVASUB_V : VSALU_IV_V_X<"vasub", 0b100110>;
+defm TH_VAADD_V : VSALU_IV_V_X_I<"th.vaadd", 0b100100>;
+defm TH_VASUB_V : VSALU_IV_V_X<"th.vasub", 0b100110>;
// Vector Single-Width Fractional Multiply with Rounding and Saturation
-defm XVSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>;
+defm TH_VSMUL_V : VSMUL_IV_V_X<"th.vsmul", 0b100111>;
// Vector Widening Saturating Scaled Multiply-Add
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
-defm XVWSMACCU_V : VWSMAC_V_X<"vwsmaccu", 0b111100>;
-defm XVWSMACC_V : VWSMAC_V_X<"vwsmacc", 0b111101>;
-defm XVWSMACCSU_V : VWSMAC_V_X<"vwsmaccsu", 0b111110>;
-defm XVWSMACCUS_V : VWSMAC_X<"vwsmaccus", 0b111111>;
+defm TH_VWSMACCU_V : TH_VWSMAC_V_X<"th.vwsmaccu", 0b111100>;
+defm TH_VWSMACC_V : TH_VWSMAC_V_X<"th.vwsmacc", 0b111101>;
+defm TH_VWSMACCSU_V : TH_VWSMAC_V_X<"th.vwsmaccsu", 0b111110>;
+defm TH_VWSMACCUS_V : TH_VWSMAC_X<"th.vwsmaccus", 0b111111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
// Vector Single-Width Scaling Shift Instructions
-defm XVSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010>;
-defm XVSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011>;
+defm TH_VSSRL_V : VSSHF_IV_V_X_I<"th.vssrl", 0b101010>;
+defm TH_VSSRA_V : VSSHF_IV_V_X_I<"th.vssra", 0b101011>;
// Vector Narrowing Fixed-Point Clip Instructions
let Constraints = "@earlyclobber $vd" in {
-defm XVNCLIPU_W : XVNCLP_IV_V_X_I<"vnclipu", 0b101110>;
-defm XVNCLIP_W : XVNCLP_IV_V_X_I<"vnclip", 0b101111>;
+defm TH_VNCLIPU_W : TH_VNCLP_IV_V_X_I<"th.vnclipu", 0b101110>;
+defm TH_VNCLIP_W : TH_VNCLP_IV_V_X_I<"th.vnclip", 0b101111>;
} // Constraints = "@earlyclobber $vd"
} // Predicates = [HasVendorXTHeadV]
let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
// Vector Single-Width Floating-Point Add/Subtract Instructions
let Uses = [FRM], mayRaiseFPException = true in {
-defm XVFADD_V : VALU_FV_V_F<"vfadd", 0b000000>;
-defm XVFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>;
-defm XVFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>;
+defm TH_VFADD_V : VALU_FV_V_F<"th.vfadd", 0b000000>;
+defm TH_VFSUB_V : VALU_FV_V_F<"th.vfsub", 0b000010>;
+defm TH_VFRSUB_V : VALU_FV_F<"th.vfrsub", 0b100111>;
}
// Vector Widening Floating-Point Add/Subtract Instructions
@@ -461,109 +584,109 @@ let Constraints = "@earlyclobber $vd",
Uses = [FRM],
mayRaiseFPException = true in {
let RVVConstraint = WidenV in {
-defm XVFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000, "v">;
-defm XVFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010, "v">;
+defm TH_VFWADD_V : VWALU_FV_V_F<"th.vfwadd", 0b110000, "v">;
+defm TH_VFWSUB_V : VWALU_FV_V_F<"th.vfwsub", 0b110010, "v">;
} // RVVConstraint = WidenV
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
let RVVConstraint = WidenW in {
-defm XVFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">;
-defm XVFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">;
+defm TH_VFWADD_W : VWALU_FV_V_F<"th.vfwadd", 0b110100, "w">;
+defm TH_VFWSUB_W : VWALU_FV_V_F<"th.vfwsub", 0b110110, "w">;
} // RVVConstraint = WidenW
} // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true
// Vector Single-Width Floating-Point Multiply/Divide Instructions
let Uses = [FRM], mayRaiseFPException = true in {
-defm XVFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>;
-defm XVFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>;
-defm XVFRDIV_V : VDIV_FV_F<"vfrdiv", 0b100001>;
+defm TH_VFMUL_V : VMUL_FV_V_F<"th.vfmul", 0b100100>;
+defm TH_VFDIV_V : VDIV_FV_V_F<"th.vfdiv", 0b100000>;
+defm TH_VFRDIV_V : VDIV_FV_F<"th.vfrdiv", 0b100001>;
}
// Vector Widening Floating-Point Multiply
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
Uses = [FRM], mayRaiseFPException = true in {
-defm XVFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>;
+defm TH_VFWMUL_V : VWMUL_FV_V_F<"th.vfwmul", 0b111000>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
let Uses = [FRM], mayRaiseFPException = true in {
-defm XVFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>;
-defm XVFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>;
-defm XVFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>;
-defm XVFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>;
-defm XVFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>;
-defm XVFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>;
-defm XVFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>;
-defm XVFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>;
+defm TH_VFMACC_V : VMAC_FV_V_F<"th.vfmacc", 0b101100>;
+defm TH_VFNMACC_V : VMAC_FV_V_F<"th.vfnmacc", 0b101101>;
+defm TH_VFMSAC_V : VMAC_FV_V_F<"th.vfmsac", 0b101110>;
+defm TH_VFNMSAC_V : VMAC_FV_V_F<"th.vfnmsac", 0b101111>;
+defm TH_VFMADD_V : VMAC_FV_V_F<"th.vfmadd", 0b101000>;
+defm TH_VFNMADD_V : VMAC_FV_V_F<"th.vfnmadd", 0b101001>;
+defm TH_VFMSUB_V : VMAC_FV_V_F<"th.vfmsub", 0b101010>;
+defm TH_VFNMSUB_V : VMAC_FV_V_F<"th.vfnmsub", 0b101011>;
}
// Vector Widening Floating-Point Fused Multiply-Add Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
Uses = [FRM], mayRaiseFPException = true in {
-defm XVFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>;
-defm XVFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>;
-defm XVFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>;
-defm XVFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>;
+defm TH_VFWMACC_V : VWMAC_FV_V_F<"th.vfwmacc", 0b111100>;
+defm TH_VFWNMACC_V : VWMAC_FV_V_F<"th.vfwnmacc", 0b111101>;
+defm TH_VFWMSAC_V : VWMAC_FV_V_F<"th.vfwmsac", 0b111110>;
+defm TH_VFWNMSAC_V : VWMAC_FV_V_F<"th.vfwnmsac", 0b111111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
// Vector Floating-Point Square-Root Instruction
let Uses = [FRM], mayRaiseFPException = true in {
-defm XVFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
+defm TH_VFSQRT_V : VSQR_FV_VS2<"th.vfsqrt.v", 0b100011, 0b00000>;
}
// Vector Floating-Point MIN/MAX Instructions
let mayRaiseFPException = true in {
-defm XVFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>;
-defm XVFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>;
+defm TH_VFMIN_V : VCMP_FV_V_F<"th.vfmin", 0b000100>;
+defm TH_VFMAX_V : VCMP_FV_V_F<"th.vfmax", 0b000110>;
}
// Vector Floating-Point Sign-Injection Instructions
-defm XVFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>;
-defm XVFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>;
-defm XVFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>;
+defm TH_VFSGNJ_V : VSGNJ_FV_V_F<"th.vfsgnj", 0b001000>;
+defm TH_VFSGNJN_V : VSGNJ_FV_V_F<"th.vfsgnjn", 0b001001>;
+defm TH_VFSGNJX_V : VSGNJ_FV_V_F<"th.vfsgnjx", 0b001010>;
// Vector Floating-Point Compare Instructions
let RVVConstraint = NoConstraint, mayRaiseFPException = true in {
-defm XVMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>;
-defm XVMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>;
-defm XVMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>;
-defm XVMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>;
-defm XVMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>;
-defm XVMFGE_V : VCMP_FV_F<"vmfge", 0b011111>;
-defm XVMFORD_V : VCMP_FV_V_F<"vmford", 0b011010>;
+defm TH_VMFEQ_V : VCMP_FV_V_F<"th.vmfeq", 0b011000>;
+defm TH_VMFNE_V : VCMP_FV_V_F<"th.vmfne", 0b011100>;
+defm TH_VMFLT_V : VCMP_FV_V_F<"th.vmflt", 0b011011>;
+defm TH_VMFLE_V : VCMP_FV_V_F<"th.vmfle", 0b011001>;
+defm TH_VMFGT_V : VCMP_FV_F<"th.vmfgt", 0b011101>;
+defm TH_VMFGE_V : VCMP_FV_F<"th.vmfge", 0b011111>;
+defm TH_VMFORD_V : VCMP_FV_V_F<"th.vmford", 0b011010>;
} // RVVConstraint = NoConstraint, mayRaiseFPException = true
// Vector Floating-Point Classify Instruction
-defm XVFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
+defm TH_VFCLASS_V : VCLS_FV_VS2<"th.vfclass.v", 0b100011, 0b10000>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// Vector Floating-Point Merge Instruction
let vm = 0 in
-def XVFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
- (ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
- "vfmerge.vfm", "$vd, $vs2, $rs1, v0">,
- Sched<[WriteVFMergeV_WorstCase, ReadVFMergeV_WorstCase,
- ReadVFMergeF_WorstCase, ReadVMask]>;
+def TH_VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
+ (ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
+ "th.vfmerge.vfm", "$vd, $vs2, $rs1, v0">,
+ Sched<[WriteVFMergeV_WorstCase, ReadVFMergeV_WorstCase,
+ ReadVFMergeF_WorstCase, ReadVMask]>;
// Vector Floating-Point Move Instruction
let RVVConstraint = NoConstraint in
let vm = 1, vs2 = 0 in
-def XVFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
- (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">,
- Sched<[WriteVFMovV_WorstCase, ReadVFMovF_WorstCase]>;
+def TH_VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
+ (ins FPR32:$rs1), "th.vfmv.v.f", "$vd, $rs1">,
+ Sched<[WriteVFMovV_WorstCase, ReadVFMovF_WorstCase]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
// Single-Width Floating-Point/Integer Type-Convert Instructions
let mayRaiseFPException = true in {
let Uses = [FRM] in {
-defm XVFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
-defm XVFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
-defm XVFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
-defm XVFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
+defm TH_VFCVT_XU_F_V : VCVTI_FV_VS2<"th.vfcvt.xu.f.v", 0b100010, 0b00000>;
+defm TH_VFCVT_X_F_V : VCVTI_FV_VS2<"th.vfcvt.x.f.v", 0b100010, 0b00001>;
+defm TH_VFCVT_F_XU_V : VCVTF_IV_VS2<"th.vfcvt.f.xu.v", 0b100010, 0b00010>;
+defm TH_VFCVT_F_X_V : VCVTF_IV_VS2<"th.vfcvt.f.x.v", 0b100010, 0b00011>;
}
} // mayRaiseFPException = true
@@ -571,22 +694,22 @@ defm XVFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt,
mayRaiseFPException = true in {
let Uses = [FRM] in {
-defm XVFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
-defm XVFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
+defm TH_VFWCVT_XU_F_V : VWCVTI_FV_VS2<"th.vfwcvt.xu.f.v", 0b100010, 0b01000>;
+defm TH_VFWCVT_X_F_V : VWCVTI_FV_VS2<"th.vfwcvt.x.f.v", 0b100010, 0b01001>;
}
-defm XVFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
-defm XVFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
-defm XVFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
+defm TH_VFWCVT_F_XU_V : VWCVTF_IV_VS2<"th.vfwcvt.f.xu.v", 0b100010, 0b01010>;
+defm TH_VFWCVT_F_X_V : VWCVTF_IV_VS2<"th.vfwcvt.f.x.v", 0b100010, 0b01011>;
+defm TH_VFWCVT_F_F_V : VWCVTF_FV_VS2<"th.vfwcvt.f.f.v", 0b100010, 0b01100>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
// Narrowing Floating-Point/Integer Type-Convert Instructions
let Constraints = "@earlyclobber $vd", mayRaiseFPException = true in {
let Uses = [FRM] in {
-defm XVFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.v", 0b100010, 0b10000>;
-defm XVFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.v", 0b100010, 0b10001>;
-defm XVFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.v", 0b100010, 0b10010>;
-defm XVFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.v", 0b100010, 0b10011>;
-defm XVFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.v", 0b100010, 0b10100>;
+defm TH_VFNCVT_XU_F_W : VNCVTI_FV_VS2<"th.vfncvt.xu.f.v", 0b100010, 0b10000>;
+defm TH_VFNCVT_X_F_W : VNCVTI_FV_VS2<"th.vfncvt.x.f.v", 0b100010, 0b10001>;
+defm TH_VFNCVT_F_XU_W : VNCVTF_IV_VS2<"th.vfncvt.f.xu.v", 0b100010, 0b10010>;
+defm TH_VFNCVT_F_X_W : VNCVTF_IV_VS2<"th.vfncvt.f.x.v", 0b100010, 0b10011>;
+defm TH_VFNCVT_F_F_W : VNCVTF_FV_VS2<"th.vfncvt.f.f.v", 0b100010, 0b10100>;
}
} // Constraints = "@earlyclobber $vd", mayRaiseFPException = true
} // Predicates = [HasVendorXTHeadV, HasStdExtF]
@@ -594,14 +717,14 @@ defm XVFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.v", 0b100010, 0b10100>;
let Predicates = [HasVendorXTHeadV] in {
// Vector Single-Width Integer Reduction Instructions
let RVVConstraint = NoConstraint in {
-defm XVREDSUM : VRED_MV_V<"vredsum", 0b000000>;
-defm XVREDMAXU : VRED_MV_V<"vredmaxu", 0b000110>;
-defm XVREDMAX : VRED_MV_V<"vredmax", 0b000111>;
-defm XVREDMINU : VRED_MV_V<"vredminu", 0b000100>;
-defm XVREDMIN : VRED_MV_V<"vredmin", 0b000101>;
-defm XVREDAND : VRED_MV_V<"vredand", 0b000001>;
-defm XVREDOR : VRED_MV_V<"vredor", 0b000010>;
-defm XVREDXOR : VRED_MV_V<"vredxor", 0b000011>;
+defm TH_VREDSUM : VRED_MV_V<"th.vredsum", 0b000000>;
+defm TH_VREDMAXU : VRED_MV_V<"th.vredmaxu", 0b000110>;
+defm TH_VREDMAX : VRED_MV_V<"th.vredmax", 0b000111>;
+defm TH_VREDMINU : VRED_MV_V<"th.vredminu", 0b000100>;
+defm TH_VREDMIN : VRED_MV_V<"th.vredmin", 0b000101>;
+defm TH_VREDAND : VRED_MV_V<"th.vredand", 0b000001>;
+defm TH_VREDOR : VRED_MV_V<"th.vredor", 0b000010>;
+defm TH_VREDXOR : VRED_MV_V<"th.vredxor", 0b000011>;
} // RVVConstraint = NoConstraint
// Vector Widening Integer Reduction Instructions
@@ -610,8 +733,8 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
-defm XVWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>;
-defm XVWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>;
+defm TH_VWREDSUMU : VWRED_IV_V<"th.vwredsumu", 0b110000>;
+defm TH_VWREDSUM : VWRED_IV_V<"th.vwredsum", 0b110001>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
} // Predicates = [HasVendorXTHeadV]
@@ -620,12 +743,12 @@ let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
// Vector Single-Width Floating-Point Reduction Instructions
let RVVConstraint = NoConstraint in {
let Uses = [FRM], mayRaiseFPException = true in {
-defm XVFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>;
-defm XVFREDUSUM : VRED_FV_V<"vfredsum", 0b000001>;
+defm TH_VFREDOSUM : VREDO_FV_V<"th.vfredosum", 0b000011>;
+defm TH_VFREDUSUM : VRED_FV_V<"th.vfredsum", 0b000001>;
}
let mayRaiseFPException = true in {
-defm XVFREDMAX : VRED_FV_V<"vfredmax", 0b000111>;
-defm XVFREDMIN : VRED_FV_V<"vfredmin", 0b000101>;
+defm TH_VFREDMAX : VRED_FV_V<"th.vfredmax", 0b000111>;
+defm TH_VFREDMIN : VRED_FV_V<"th.vfredmin", 0b000101>;
}
} // RVVConstraint = NoConstraint
@@ -636,8 +759,8 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
let Uses = [FRM], mayRaiseFPException = true in {
-defm XVFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>;
-defm XVFWREDUSUM : VWRED_FV_V<"vfwredsum", 0b110001>;
+defm TH_VFWREDOSUM : VWREDO_FV_V<"th.vfwredosum", 0b110011>;
+defm TH_VFWREDUSUM : VWRED_FV_V<"th.vfwredsum", 0b110001>;
}
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
} // Predicates = [HasVendorXTHeadV, HasStdExtF]
@@ -645,69 +768,69 @@ defm XVFWREDUSUM : VWRED_FV_V<"vfwredsum", 0b110001>;
let Predicates = [HasVendorXTHeadV] in {
// Vector Mask-Register Logical Instructions
let RVVConstraint = NoConstraint in {
-defm XVMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">;
-defm XVMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">;
-defm XVMANDN_M : VMALU_MV_Mask<"vmandnot", 0b011000, "m">;
-defm XVMXOR_M : VMALU_MV_Mask<"vmxor", 0b011011, "m">;
-defm XVMOR_M : VMALU_MV_Mask<"vmor", 0b011010, "m">;
-defm XVMNOR_M : VMALU_MV_Mask<"vmnor", 0b011110, "m">;
-defm XVMORN_M : VMALU_MV_Mask<"vmornot", 0b011100, "m">;
-defm XVMXNOR_M : VMALU_MV_Mask<"vmxnor", 0b011111, "m">;
+defm TH_VMAND_M : VMALU_MV_Mask<"th.vmand", 0b011001, "m">;
+defm TH_VMNAND_M : VMALU_MV_Mask<"th.vmnand", 0b011101, "m">;
+defm TH_VMANDN_M : VMALU_MV_Mask<"th.vmandnot", 0b011000, "m">;
+defm TH_VMXOR_M : VMALU_MV_Mask<"th.vmxor", 0b011011, "m">;
+defm TH_VMOR_M : VMALU_MV_Mask<"th.vmor", 0b011010, "m">;
+defm TH_VMNOR_M : VMALU_MV_Mask<"th.vmnor", 0b011110, "m">;
+defm TH_VMORN_M : VMALU_MV_Mask<"th.vmornot", 0b011100, "m">;
+defm TH_VMXNOR_M : VMALU_MV_Mask<"th.vmxnor", 0b011111, "m">;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
RVVConstraint = NoConstraint in {
// Vector mask population count vmpopc
-def XVMPOPC_M : RVInstV<0b010100, 0b00000, OPMVV, (outs GPR:$vd),
- (ins VR:$vs2, VMaskOp:$vm),
- "vmpopc.m", "$vd, $vs2$vm">,
- Sched<[WriteVMPopV_WorstCase, ReadVMPopV_WorstCase,
- ReadVMask]>;
+def TH_VMPOPC_M : RVInstV<0b010100, 0b00000, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, VMaskOp:$vm),
+ "th.vmpopc.m", "$vd, $vs2$vm">,
+ Sched<[WriteVMPopV_WorstCase, ReadVMPopV_WorstCase,
+ ReadVMask]>;
// vmfirst find-first-set mask bit
-def XVMFIRST_M : RVInstV<0b010101, 0b00000, OPMVV, (outs GPR:$vd),
- (ins VR:$vs2, VMaskOp:$vm),
- "vmfirst.m", "$vd, $vs2$vm">,
- Sched<[WriteVMFFSV_WorstCase, ReadVMFFSV_WorstCase,
- ReadVMask]>;
+def TH_VMFIRST_M : RVInstV<0b010101, 0b00000, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, VMaskOp:$vm),
+ "th.vmfirst.m", "$vd, $vs2$vm">,
+ Sched<[WriteVMFFSV_WorstCase, ReadVMFFSV_WorstCase,
+ ReadVMask]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
// vmsbf.m set-before-first mask bit
-defm XVMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010110, 0b00001>;
+defm TH_VMSBF_M : VMSFS_MV_V<"th.vmsbf.m", 0b010110, 0b00001>;
// vmsif.m set-including-first mask bit
-defm XVMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010110, 0b00011>;
+defm TH_VMSIF_M : VMSFS_MV_V<"th.vmsif.m", 0b010110, 0b00011>;
// vmsof.m set-only-first mask bit
-defm XVMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010110, 0b00010>;
+defm TH_VMSOF_M : VMSFS_MV_V<"th.vmsof.m", 0b010110, 0b00010>;
// Vector Iota Instruction
- defm XVIOTA_M : VMIOT_MV_V<"viota.m", 0b010110, 0b10000>;
+defm TH_VIOTA_M : VIOTA_MV_V<"th.viota.m", 0b010110, 0b10000>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// Vector Element Index Instruction
let vs2 = 0 in
-def XVID_V : RVInstV<0b010110, 0b10001, OPMVV, (outs VR:$vd),
- (ins VMaskOp:$vm), "vid.v", "$vd$vm">,
- Sched<[WriteVMIdxV_WorstCase, ReadVMask]>;
+def TH_VID_V : RVInstV<0b010110, 0b10001, OPMVV, (outs VR:$vd),
+ (ins VMaskOp:$vm),
+ "th.vid.v", "$vd$vm">,
+ SchedNullaryMC<"WriteVIdxV">;
let vm = 1, RVVConstraint = NoConstraint in {
// Integer Extract Instruction
-def XVEXT_X_V : RVInstVX<0b001100, OPMVV, (outs GPR:$vd),
- (ins VR:$vs2, GPR:$rs1),
- "vext.x.v", "$vd, $vs2, $rs1">,
- Sched<[WriteVIMovVX, ReadVIMovVX,
- ReadVIMovXX]>;
+def TH_VEXT_X_V : RVInstVX<0b001100, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, GPR:$rs1),
+ "th.vext.x.v", "$vd, $vs2, $rs1">,
+ Sched<[WriteVIMovVX, ReadVIMovVX, ReadVIMovXX]>;
// Integer Scalar Move Instruction
let Constraints = "$vd = $vd_wb" in
-def XVMV_S_X : RVInstV2<0b001101, 0b00000, OPMVX, (outs VR:$vd_wb),
- (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
- Sched<[WriteVIMovXV, ReadVIMovXV,
- ReadVIMovXX]>;
+def TH_VMV_S_X : RVInstV2<0b001101, 0b00000, OPMVX, (outs VR:$vd_wb),
+ (ins VR:$vd, GPR:$rs1),
+ "th.vmv.s.x", "$vd, $rs1">,
+ Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXTHeadV]
@@ -716,14 +839,15 @@ let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
RVVConstraint = NoConstraint in {
// Floating-Point Scalar Move Instructions
-def XVFMV_F_S : RVInstV<0b001100, 0b00000, OPFVV, (outs FPR32:$vd),
- (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
- Sched<[WriteVFMovVF, ReadVFMovVF]>;
+def TH_VFMV_F_S : RVInstV<0b001100, 0b00000, OPFVV, (outs FPR32:$vd),
+ (ins VR:$vs2),
+ "th.vfmv.f.s", "$vd, $vs2">,
+ Sched<[WriteVFMovVF, ReadVFMovVF]>;
let Constraints = "$vd = $vd_wb" in
-def XVFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb),
- (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
- Sched<[WriteVFMovFV, ReadVFMovFV,
- ReadVFMovFX]>;
+def TH_VFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb),
+ (ins VR:$vd, FPR32:$rs1),
+ "th.vfmv.s.f", "$vd, $rs1">,
+ Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
} // Predicates = [HasVendorXTHeadV, HasStdExtF]
@@ -731,20 +855,118 @@ def XVFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb),
let Predicates = [HasVendorXTHeadV] in {
// Vector Slide Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
-defm XVSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110>;
-defm XVSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
+defm TH_VSLIDEUP_V : VSLD_IV_X_I<"th.vslideup", 0b001110>;
+defm TH_VSLIDE1UP_V : VSLD1_MV_X<"th.vslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
-defm XVSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111>;
-defm XVSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
+defm TH_VSLIDEDOWN_V : VSLD_IV_X_I<"th.vslidedown", 0b001111>;
+defm TH_VSLIDE1DOWN_V : VSLD1_MV_X<"th.vslide1down", 0b001111>;
// Vector Register Gather Instruction
let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
-defm XVRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>;
+defm TH_VRGATHER_V : VGTR_IV_V_X_I<"th.vrgather", 0b001100>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
// Vector Compress Instruction
let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
-defm XVCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
+defm TH_VCOMPRESS_V : VCPR_MV_Mask<"th.vcompress", 0b010111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
} // Predicates = [HasVendorXTHeadV]
-} // AsmVariantName = "RVV0p71", DecoderNamespace = "RVV0p71"
+} // DecoderNamespace = "RVV0p71"
+
+// Pseudo instructions
+let Predicates = [HasVendorXTHeadV] in {
+// Vector Integer Comparison Instructions
+def : InstAlias<"th.vmsgtu.vv $vd, $va, $vb$vm",
+ (TH_VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"th.vmsgt.vv $vd, $va, $vb$vm",
+ (TH_VMSLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"th.vmsgeu.vv $vd, $va, $vb$vm",
+ (TH_VMSLEU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"th.vmsge.vv $vd, $va, $vb$vm",
+ (TH_VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+
+// These pseudos need to be handled in RISCVAsmParser::processInstruction
+let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0,
+ mayStore = 0 in {
+// For unsigned comparisons we need to special case 0 immediate to maintain
+// the always true/false semantics we would invert if we just decremented the
+// immediate like we do for signed. To match the GNU assembler we will use
+// vmseq/vmsne.vv with the same register for both operands which we can't do
+// from an InstAlias.
+def PseudoTH_VMSGEU_VI : Pseudo<(outs VR:$vd),
+ (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm),
+ [], "th.vmsgeu.vi", "$vd, $vs2, $imm$vm">;
+def PseudoTH_VMSLTU_VI : Pseudo<(outs VR:$vd),
+ (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm),
+ [], "th.vmsltu.vi", "$vd, $vs2, $imm$vm">;
+// Handle signed with pseudos as well for more consistency in the
+// implementation.
+def PseudoTH_VMSGE_VI : Pseudo<(outs VR:$vd),
+ (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm),
+ [], "th.vmsge.vi", "$vd, $vs2, $imm$vm">;
+def PseudoTH_VMSLT_VI : Pseudo<(outs VR:$vd),
+ (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm),
+ [], "th.vmslt.vi", "$vd, $vs2, $imm$vm">;
+}
+
+// These pseudos need to be handled in RISCVAsmParser::processInstruction
+let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0,
+ mayStore = 0 in {
+def PseudoTH_VMSGEU_VX : Pseudo<(outs VR:$vd),
+ (ins VR:$vs2, GPR:$rs1),
+ [], "th.vmsgeu.vx", "$vd, $vs2, $rs1">;
+def PseudoTH_VMSGE_VX : Pseudo<(outs VR:$vd),
+ (ins VR:$vs2, GPR:$rs1),
+ [], "th.vmsge.vx", "$vd, $vs2, $rs1">;
+def PseudoTH_VMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd),
+ (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
+ [], "th.vmsgeu.vx", "$vd, $vs2, $rs1$vm">;
+def PseudoTH_VMSGE_VX_M : Pseudo<(outs VRNoV0:$vd),
+ (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
+ [], "th.vmsge.vx", "$vd, $vs2, $rs1$vm">;
+def PseudoTH_VMSGEU_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch),
+ (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
+ [], "th.vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">;
+def PseudoTH_VMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch),
+ (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
+ [], "th.vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">;
+} // isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+
+// Vector Floating-Point Compare Instructions
+def : InstAlias<"th.vmfgt.vv $vd, $va, $vb$vm",
+ (TH_VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"th.vmfge.vv $vd, $va, $vb$vm",
+ (TH_VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
+
+// Vector Bitwise Logical Instructions
+def : InstAlias<"th.vnot.v $vd, $vs$vm",
+ (TH_VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>;
+def : InstAlias<"th.vnot.v $vd, $vs",
+ (TH_VXOR_VI VR:$vd, VR:$vs, -1, zero_reg)>;
+
+// Vector Widening Integer Add/Subtract
+def : InstAlias<"th.vwcvt.x.x.v $vd, $vs$vm",
+ (TH_VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
+def : InstAlias<"th.vwcvt.x.x.v $vd, $vs",
+ (TH_VWADD_VX VR:$vd, VR:$vs, X0, zero_reg)>;
+def : InstAlias<"th.vwcvtu.x.x.v $vd, $vs$vm",
+ (TH_VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
+def : InstAlias<"th.vwcvtu.x.x.v $vd, $vs",
+ (TH_VWADDU_VX VR:$vd, VR:$vs, X0, zero_reg)>;
+
+// Integer Extract Instruction
+def : InstAlias<"th.vmv.x.s $rd, $vs",
+ (TH_VEXT_X_V GPR:$rd, VR:$vs, X0)>;
+
+// Vector Mask-Register Logical Instructions
+def : InstAlias<"th.vmcpy.m $vd, $vs",
+ (TH_VMAND_MM VR:$vd, VR:$vs, VR:$vs)>;
+def : InstAlias<"th.vmclr.m $vd",
+ (TH_VMXOR_MM VR:$vd, VR:$vd, VR:$vd)>;
+def : InstAlias<"th.vmset.m $vd",
+ (TH_VMXNOR_MM VR:$vd, VR:$vd, VR:$vd)>;
+def : InstAlias<"th.vmnot.m $vd, $vs",
+ (TH_VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>;
+
+} // Predicates = [HasVendorXTHeadV]
diff --git a/llvm/test/MC/RISCV/xtheadvector/add.s b/llvm/test/MC/RISCV/xtheadvector/add.s
index a1735229f64715..898ae52b71da6c 100644
--- a/llvm/test/MC/RISCV/xtheadvector/add.s
+++ b/llvm/test/MC/RISCV/xtheadvector/add.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vadd.vv v8, v4, v20, v0.t
diff --git a/llvm/test/MC/RISCV/xtheadvector/and.s b/llvm/test/MC/RISCV/xtheadvector/and.s
index 6cff7f853ea985..871e29b30129db 100644
--- a/llvm/test/MC/RISCV/xtheadvector/and.s
+++ b/llvm/test/MC/RISCV/xtheadvector/and.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vand.vv v8, v4, v20, v0.t
diff --git a/llvm/test/MC/RISCV/xtheadvector/clip.s b/llvm/test/MC/RISCV/xtheadvector/clip.s
index 30d90c89242b74..5431bebc12deaf 100644
--- a/llvm/test/MC/RISCV/xtheadvector/clip.s
+++ b/llvm/test/MC/RISCV/xtheadvector/clip.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vnclipu.vv v8, v4, v20, v0.t
diff --git a/llvm/test/MC/RISCV/xtheadvector/compare.s b/llvm/test/MC/RISCV/xtheadvector/compare.s
index 527598c0b383e1..0a8c2a47623f45 100644
--- a/llvm/test/MC/RISCV/xtheadvector/compare.s
+++ b/llvm/test/MC/RISCV/xtheadvector/compare.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vmslt.vv v0, v4, v20, v0.t
diff --git a/llvm/test/MC/RISCV/xtheadvector/mv.s b/llvm/test/MC/RISCV/xtheadvector/mv.s
index f20770db12fbf4..88cca23d84f044 100644
--- a/llvm/test/MC/RISCV/xtheadvector/mv.s
+++ b/llvm/test/MC/RISCV/xtheadvector/mv.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vmv.v.v v8, v20
diff --git a/llvm/test/MC/RISCV/xtheadvector/or.s b/llvm/test/MC/RISCV/xtheadvector/or.s
index e215453ecbac3a..70826b02fe996f 100644
--- a/llvm/test/MC/RISCV/xtheadvector/or.s
+++ b/llvm/test/MC/RISCV/xtheadvector/or.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vor.vv v8, v4, v20, v0.t
diff --git a/llvm/test/MC/RISCV/xtheadvector/others.s b/llvm/test/MC/RISCV/xtheadvector/others.s
index 6ff5ab3e025e3f..64024a849a7e59 100644
--- a/llvm/test/MC/RISCV/xtheadvector/others.s
+++ b/llvm/test/MC/RISCV/xtheadvector/others.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex -M no-aliases - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vmerge.vvm v8, v4, v20, v0
diff --git a/llvm/test/MC/RISCV/xtheadvector/shift.s b/llvm/test/MC/RISCV/xtheadvector/shift.s
index eee3b1eeb8c71b..d595bb9b8bb689 100644
--- a/llvm/test/MC/RISCV/xtheadvector/shift.s
+++ b/llvm/test/MC/RISCV/xtheadvector/shift.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vsll.vv v8, v4, v20, v0.t
diff --git a/llvm/test/MC/RISCV/xtheadvector/sub.s b/llvm/test/MC/RISCV/xtheadvector/sub.s
index 7d65ad92175b5c..0709d6f9a6c8cc 100644
--- a/llvm/test/MC/RISCV/xtheadvector/sub.s
+++ b/llvm/test/MC/RISCV/xtheadvector/sub.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vsub.vv v8, v4, v20, v0.t
diff --git a/llvm/test/MC/RISCV/xtheadvector/vsetvl.s b/llvm/test/MC/RISCV/xtheadvector/vsetvl.s
index b865bdbd39a49d..a218c9c497e81a 100644
--- a/llvm/test/MC/RISCV/xtheadvector/vsetvl.s
+++ b/llvm/test/MC/RISCV/xtheadvector/vsetvl.s
@@ -3,7 +3,7 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
-# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
diff --git a/llvm/test/MC/RISCV/xtheadvector/xor.s b/llvm/test/MC/RISCV/xtheadvector/xor.s
index 2d4a839bf80db8..293e7a385aa292 100644
--- a/llvm/test/MC/RISCV/xtheadvector/xor.s
+++ b/llvm/test/MC/RISCV/xtheadvector/xor.s
@@ -3,6 +3,9 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
th.vxor.vv v8, v4, v20, v0.t
>From 471a6fd54d34a3ca02f372d2d49a3110bea07cbe Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Mon, 4 Mar 2024 13:28:46 +0800
Subject: [PATCH 3/9] fix RISCVInstPrinter for XTHeadVector
upstream change: c532ba4edd7ad7675ba450ba43268aa9e7bda46b
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 07fe9a26ec4a6f..7f9f72189cef46 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -224,7 +224,7 @@ void RISCVInstPrinter::printXTHeadVTypeI(const MCInst *MI, unsigned OpNo,
// Print the raw immediate for reserved values: vsew[2:0]=0b1xx,
// or non-zero in bits 7 and above.
if ((VSEW & 0x4) || (Imm >> 7) != 0) {
- O << Imm;
+ O << formatImm(Imm);
return;
}
// Print the text form.
>From 57baab91f5af8a92246dd9fde65cef0465a981aa Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Mon, 4 Mar 2024 14:24:00 +0800
Subject: [PATCH 4/9] port MC test from GCC
upstream change: 44000181fd53c8e100acad55e99e89403d64daf8
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 168 +-
.../lib/Target/RISCV/RISCVInstrInfoXTHeadV.td | 9 +-
llvm/test/MC/RISCV/xtheadvector/fmacc.s | 300 +
llvm/test/MC/RISCV/xtheadvector/macc.s | 273 +
.../test/MC/RISCV/xtheadvector/vector-insns.s | 6856 +++++++++++++++++
5 files changed, 7558 insertions(+), 48 deletions(-)
create mode 100644 llvm/test/MC/RISCV/xtheadvector/fmacc.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/macc.s
create mode 100644 llvm/test/MC/RISCV/xtheadvector/vector-insns.s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6e39ecea0b770f..32d08cfeafe2cd 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -163,6 +163,13 @@ class RISCVAsmParser : public MCTargetAsmParser {
// Helper to emit pseudo vmsge{u}.vx instruction.
void emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, MCStreamer &Out);
+ // Helper to emit pseudo vmsge{u}.vi instruction.
+ void emitVMSGE_VI(MCInst &Inst, unsigned Opcode, unsigned OpcodeImmIs0,
+ SMLoc IDLoc, MCStreamer &Out, bool IsSigned);
+
+ // Helper to emit pseudo vmsge{u}.vx instruction for XTHeadV extension.
+ void emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, MCStreamer &Out);
+
// Checks that a PseudoAddTPRel is using x4/tp in its second input operand.
// Enforcing this using a restricted register class for the second input
// operand of PseudoAddTPRel results in a poor diagnostic due to the fact
@@ -3419,6 +3426,92 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
}
}
+
+void RISCVAsmParser::emitVMSGE_VI(MCInst &Inst, unsigned Opcode,
+ unsigned OpcodeImmIs0, SMLoc IDLoc,
+ MCStreamer &Out, bool IsSigned) {
+ int64_t Imm = Inst.getOperand(2).getImm();
+ if (IsSigned) {
+ // These instructions are signed and so is immediate so we can subtract one.
+ emitToStreamer(Out, MCInstBuilder(Opcode)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(1))
+ .addImm(Imm - 1)
+ .addOperand(Inst.getOperand(3)));
+ } else {
+ // Unsigned comparisons are tricky because the immediate is signed. If the
+ // immediate is 0 we can't just subtract one. vmsltu.vi v0, v1, 0 is always
+ // false, but vmsle.vi v0, v1, -1 is always true. Instead we use
+ // vmsne v0, v1, v1 which is always false.
+ if (Imm == 0) {
+ emitToStreamer(Out, MCInstBuilder(OpcodeImmIs0)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(1))
+ .addOperand(Inst.getOperand(1))
+ .addOperand(Inst.getOperand(3)));
+ } else {
+ // Other immediate values can subtract one like signed.
+ emitToStreamer(Out, MCInstBuilder(Opcode)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(1))
+ .addImm(Imm - 1)
+ .addOperand(Inst.getOperand(3)));
+ }
+ }
+}
+
+void RISCVAsmParser::emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
+ MCStreamer &Out) {
+ // https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1
+ if (Inst.getNumOperands() == 3) {
+ // unmasked va >= x
+ //
+ // pseudoinstruction: vmsge{u}.vx vd, va, x
+ // expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
+ emitToStreamer(Out, MCInstBuilder(Opcode)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(1))
+ .addOperand(Inst.getOperand(2))
+ .addReg(RISCV::NoRegister));
+ emitToStreamer(Out, MCInstBuilder(RISCV::TH_VMNAND_MM)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(0)));
+ } else if (Inst.getNumOperands() == 4) {
+ // masked va >= x, vd != v0
+ //
+ // pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
+ // expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
+ assert(Inst.getOperand(0).getReg() != RISCV::V0 &&
+ "The destination register should not be V0.");
+ emitToStreamer(Out, MCInstBuilder(Opcode)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(1))
+ .addOperand(Inst.getOperand(2))
+ .addOperand(Inst.getOperand(3)));
+ emitToStreamer(Out, MCInstBuilder(RISCV::TH_VMXOR_MM)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(0))
+ .addReg(RISCV::V0));
+ } else if (Inst.getNumOperands() == 5) {
+ // masked va >= x, any vd
+ //
+ // pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
+ // expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt
+ assert(Inst.getOperand(1).getReg() != RISCV::V0 &&
+ "The temporary vector register should not be V0.");
+ emitToStreamer(Out, MCInstBuilder(Opcode)
+ .addOperand(Inst.getOperand(1))
+ .addOperand(Inst.getOperand(2))
+ .addOperand(Inst.getOperand(3))
+ .addReg(RISCV::NoRegister));
+ emitToStreamer(Out, MCInstBuilder(RISCV::TH_VMANDN_MM)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(1)));
+ }
+}
+
bool RISCVAsmParser::checkPseudoAddTPRel(MCInst &Inst,
OperandVector &Operands) {
assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction");
@@ -3465,7 +3558,9 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
unsigned Opcode = Inst.getOpcode();
if (Opcode == RISCV::PseudoVMSGEU_VX_M_T ||
- Opcode == RISCV::PseudoVMSGE_VX_M_T) {
+ Opcode == RISCV::PseudoVMSGE_VX_M_T ||
+ Opcode == RISCV::PseudoTH_VMSGEU_VX_M_T ||
+ Opcode == RISCV::PseudoTH_VMSGE_VX_M_T) {
unsigned DestReg = Inst.getOperand(0).getReg();
unsigned TempReg = Inst.getOperand(1).getReg();
if (DestReg == TempReg) {
@@ -3707,49 +3802,40 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
emitVMSGE(Inst, RISCV::VMSLT_VX, IDLoc, Out);
return false;
case RISCV::PseudoVMSGE_VI:
- case RISCV::PseudoVMSLT_VI: {
- // These instructions are signed and so is immediate so we can subtract one
- // and change the opcode.
- int64_t Imm = Inst.getOperand(2).getImm();
- unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGE_VI ? RISCV::VMSGT_VI
- : RISCV::VMSLE_VI;
- emitToStreamer(Out, MCInstBuilder(Opc)
- .addOperand(Inst.getOperand(0))
- .addOperand(Inst.getOperand(1))
- .addImm(Imm - 1)
- .addOperand(Inst.getOperand(3)));
+ emitVMSGE_VI(Inst, RISCV::VMSGT_VI, RISCV::VMSGT_VI, IDLoc, Out, true);
+ return false;
+ case RISCV::PseudoVMSLT_VI:
+ emitVMSGE_VI(Inst, RISCV::VMSLE_VI, RISCV::VMSLE_VI, IDLoc, Out, true);
return false;
- }
case RISCV::PseudoVMSGEU_VI:
- case RISCV::PseudoVMSLTU_VI: {
- int64_t Imm = Inst.getOperand(2).getImm();
- // Unsigned comparisons are tricky because the immediate is signed. If the
- // immediate is 0 we can't just subtract one. vmsltu.vi v0, v1, 0 is always
- // false, but vmsle.vi v0, v1, -1 is always true. Instead we use
- // vmsne v0, v1, v1 which is always false.
- if (Imm == 0) {
- unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI
- ? RISCV::VMSEQ_VV
- : RISCV::VMSNE_VV;
- emitToStreamer(Out, MCInstBuilder(Opc)
- .addOperand(Inst.getOperand(0))
- .addOperand(Inst.getOperand(1))
- .addOperand(Inst.getOperand(1))
- .addOperand(Inst.getOperand(3)));
- } else {
- // Other immediate values can subtract one like signed.
- unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI
- ? RISCV::VMSGTU_VI
- : RISCV::VMSLEU_VI;
- emitToStreamer(Out, MCInstBuilder(Opc)
- .addOperand(Inst.getOperand(0))
- .addOperand(Inst.getOperand(1))
- .addImm(Imm - 1)
- .addOperand(Inst.getOperand(3)));
- }
-
+ emitVMSGE_VI(Inst, RISCV::VMSGTU_VI, RISCV::VMSEQ_VV, IDLoc, Out, false);
+ return false;
+ case RISCV::PseudoVMSLTU_VI:
+ emitVMSGE_VI(Inst, RISCV::VMSLEU_VI, RISCV::VMSNE_VV, IDLoc, Out, false);
+ return false;
+ // for XTHeadVector Extension
+ case RISCV::PseudoTH_VMSGEU_VX:
+ case RISCV::PseudoTH_VMSGEU_VX_M:
+ case RISCV::PseudoTH_VMSGEU_VX_M_T:
+ emitVMSGE_TH(Inst, RISCV::TH_VMSLTU_VX, IDLoc, Out);
+ return false;
+ case RISCV::PseudoTH_VMSGE_VX:
+ case RISCV::PseudoTH_VMSGE_VX_M:
+ case RISCV::PseudoTH_VMSGE_VX_M_T:
+ emitVMSGE_TH(Inst, RISCV::TH_VMSLT_VX, IDLoc, Out);
+ return false;
+ case RISCV::PseudoTH_VMSGE_VI:
+ emitVMSGE_VI(Inst, RISCV::TH_VMSGT_VI, RISCV::TH_VMSGT_VI, IDLoc, Out, true);
+ return false;
+ case RISCV::PseudoTH_VMSLT_VI:
+ emitVMSGE_VI(Inst, RISCV::TH_VMSLE_VI, RISCV::TH_VMSLE_VI, IDLoc, Out, true);
+ return false;
+ case RISCV::PseudoTH_VMSGEU_VI:
+ emitVMSGE_VI(Inst, RISCV::TH_VMSGTU_VI, RISCV::TH_VMSEQ_VV, IDLoc, Out, false);
+ return false;
+ case RISCV::PseudoTH_VMSLTU_VI:
+ emitVMSGE_VI(Inst, RISCV::TH_VMSLEU_VI, RISCV::TH_VMSNE_VV, IDLoc, Out, false);
return false;
- }
}
emitToStreamer(Out, Inst);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
index f9ed15c61b3cb6..70905a589a06e1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
@@ -512,12 +512,10 @@ defm TH_VMADD_V : VMAC_MV_V_X<"th.vmadd", 0b101001>;
defm TH_VNMSUB_V : VMAC_MV_V_X<"th.vnmsub", 0b101011>;
// Vector Widening Integer Multiply-Add Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
defm TH_VWMACCU_V : VWMAC_MV_V_X<"th.vwmaccu", 0b111100>;
defm TH_VWMACC_V : VWMAC_MV_V_X<"th.vwmacc", 0b111101>;
defm TH_VWMACCSU_V : VWMAC_MV_V_X<"th.vwmaccsu", 0b111110>;
defm TH_VWMACCUS_V : VWMAC_MV_X<"th.vwmaccus", 0b111111>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
// Vector Integer Merge Instructions
defm TH_VMERGE_V : VMRG_IV_V_X_I<"th.vmerge", 0b010111>;
@@ -553,12 +551,10 @@ defm TH_VASUB_V : VSALU_IV_V_X<"th.vasub", 0b100110>;
defm TH_VSMUL_V : VSMUL_IV_V_X<"th.vsmul", 0b100111>;
// Vector Widening Saturating Scaled Multiply-Add
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
defm TH_VWSMACCU_V : TH_VWSMAC_V_X<"th.vwsmaccu", 0b111100>;
defm TH_VWSMACC_V : TH_VWSMAC_V_X<"th.vwsmacc", 0b111101>;
defm TH_VWSMACCSU_V : TH_VWSMAC_V_X<"th.vwsmaccsu", 0b111110>;
defm TH_VWSMACCUS_V : TH_VWSMAC_X<"th.vwsmaccus", 0b111111>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
// Vector Single-Width Scaling Shift Instructions
defm TH_VSSRL_V : VSSHF_IV_V_X_I<"th.vssrl", 0b101010>;
@@ -623,13 +619,12 @@ defm TH_VFNMSUB_V : VMAC_FV_V_F<"th.vfnmsub", 0b101011>;
}
// Vector Widening Floating-Point Fused Multiply-Add Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,
- Uses = [FRM], mayRaiseFPException = true in {
+let Uses = [FRM], mayRaiseFPException = true in {
defm TH_VFWMACC_V : VWMAC_FV_V_F<"th.vfwmacc", 0b111100>;
defm TH_VFWNMACC_V : VWMAC_FV_V_F<"th.vfwnmacc", 0b111101>;
defm TH_VFWMSAC_V : VWMAC_FV_V_F<"th.vfwmsac", 0b111110>;
defm TH_VFWNMSAC_V : VWMAC_FV_V_F<"th.vfwnmsac", 0b111111>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true
+} // Uses = [FRM], mayRaiseFPException = true
// Vector Floating-Point Square-Root Instruction
let Uses = [FRM], mayRaiseFPException = true in {
diff --git a/llvm/test/MC/RISCV/xtheadvector/fmacc.s b/llvm/test/MC/RISCV/xtheadvector/fmacc.s
new file mode 100644
index 00000000000000..f13115ba240c28
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/fmacc.s
@@ -0,0 +1,300 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: --mattr=+f \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vfmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a b0 <unknown>
+
+th.vfmacc.vv v8, v20, v4
+# CHECK-INST: th.vfmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a b2 <unknown>
+
+th.vfmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 b0 <unknown>
+
+th.vfmacc.vf v8, fa0, v4
+# CHECK-INST: th.vfmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 b2 <unknown>
+
+th.vfnmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfnmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb4]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a b4 <unknown>
+
+th.vfnmacc.vv v8, v20, v4
+# CHECK-INST: th.vfnmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb6]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a b6 <unknown>
+
+th.vfnmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfnmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb4]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 b4 <unknown>
+
+th.vfnmacc.vf v8, fa0, v4
+# CHECK-INST: th.vfnmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb6]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 b6 <unknown>
+
+th.vfmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a b8 <unknown>
+
+th.vfmsac.vv v8, v20, v4
+# CHECK-INST: th.vfmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xba]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a ba <unknown>
+
+th.vfmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 b8 <unknown>
+
+th.vfmsac.vf v8, fa0, v4
+# CHECK-INST: th.vfmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xba]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 ba <unknown>
+
+th.vfnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a bc <unknown>
+
+th.vfnmsac.vv v8, v20, v4
+# CHECK-INST: th.vfnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a be <unknown>
+
+th.vfnmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfnmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 bc <unknown>
+
+th.vfnmsac.vf v8, fa0, v4
+# CHECK-INST: th.vfnmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 be <unknown>
+
+th.vfmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a a0 <unknown>
+
+th.vfmadd.vv v8, v20, v4
+# CHECK-INST: th.vfmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a a2 <unknown>
+
+th.vfmadd.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfmadd.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 a0 <unknown>
+
+th.vfmadd.vf v8, fa0, v4
+# CHECK-INST: th.vfmadd.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 a2 <unknown>
+
+th.vfnmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfnmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa4]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a a4 <unknown>
+
+th.vfnmadd.vv v8, v20, v4
+# CHECK-INST: th.vfnmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa6]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a a6 <unknown>
+
+th.vfnmadd.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfnmadd.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 a4 <unknown>
+
+th.vfnmadd.vf v8, fa0, v4
+# CHECK-INST: th.vfnmadd.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 a6 <unknown>
+
+th.vfmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a a8 <unknown>
+
+th.vfmsub.vv v8, v20, v4
+# CHECK-INST: th.vfmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xaa]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a aa <unknown>
+
+th.vfmsub.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfmsub.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 a8 <unknown>
+
+th.vfmsub.vf v8, fa0, v4
+# CHECK-INST: th.vfmsub.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xaa]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 aa <unknown>
+
+th.vfnmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfnmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xac]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a ac <unknown>
+
+th.vfnmsub.vv v8, v20, v4
+# CHECK-INST: th.vfnmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xae]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a ae <unknown>
+
+th.vfnmsub.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfnmsub.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 ac <unknown>
+
+th.vfnmsub.vf v8, fa0, v4
+# CHECK-INST: th.vfnmsub.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 ae <unknown>
+
+th.vfwmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfwmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a f0 <unknown>
+
+th.vfwmacc.vv v8, v20, v4
+# CHECK-INST: th.vfwmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a f2 <unknown>
+
+th.vfwmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfwmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf0]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 f0 <unknown>
+
+th.vfwmacc.vf v8, fa0, v4
+# CHECK-INST: th.vfwmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf2]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 f2 <unknown>
+
+th.vfwnmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfwnmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf4]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a f4 <unknown>
+
+th.vfwnmacc.vv v8, v20, v4
+# CHECK-INST: th.vfwnmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf6]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a f6 <unknown>
+
+th.vfwnmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfwnmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf4]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 f4 <unknown>
+
+th.vfwnmacc.vf v8, fa0, v4
+# CHECK-INST: th.vfwnmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf6]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 f6 <unknown>
+
+th.vfwmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfwmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a f8 <unknown>
+
+th.vfwmsac.vv v8, v20, v4
+# CHECK-INST: th.vfwmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfa]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a fa <unknown>
+
+th.vfwmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfwmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf8]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 f8 <unknown>
+
+th.vfwmsac.vf v8, fa0, v4
+# CHECK-INST: th.vfwmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfa]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 fa <unknown>
+
+th.vfwnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vfwnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfc]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a fc <unknown>
+
+th.vfwnmsac.vv v8, v20, v4
+# CHECK-INST: th.vfwnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfe]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 14 4a fe <unknown>
+
+th.vfwnmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: th.vfwnmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 fc <unknown>
+
+th.vfwnmsac.vf v8, fa0, v4
+# CHECK-INST: th.vfwnmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 54 45 fe <unknown>
diff --git a/llvm/test/MC/RISCV/xtheadvector/macc.s b/llvm/test/MC/RISCV/xtheadvector/macc.s
new file mode 100644
index 00000000000000..5a73f07cee2322
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/macc.s
@@ -0,0 +1,273 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d --mattr=+xtheadvector - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xb4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a b4 <unknown>
+
+th.vmacc.vv v8, v20, v4
+# CHECK-INST: th.vmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xb6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a b6 <unknown>
+
+th.vmacc.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vmacc.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xb4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 b4 <unknown>
+
+th.vmacc.vx v8, a0, v4
+# CHECK-INST: th.vmacc.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xb6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 b6 <unknown>
+
+th.vnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a bc <unknown>
+
+th.vnmsac.vv v8, v20, v4
+# CHECK-INST: th.vnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a be <unknown>
+
+th.vnmsac.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vnmsac.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 bc <unknown>
+
+th.vnmsac.vx v8, a0, v4
+# CHECK-INST: th.vnmsac.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 be <unknown>
+
+th.vmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xa4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a a4 <unknown>
+
+th.vmadd.vv v8, v20, v4
+# CHECK-INST: th.vmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xa6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a a6 <unknown>
+
+th.vmadd.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vmadd.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 a4 <unknown>
+
+th.vmadd.vx v8, a0, v4
+# CHECK-INST: th.vmadd.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 a6 <unknown>
+
+th.vnmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vnmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a ac <unknown>
+
+th.vnmsub.vv v8, v20, v4
+# CHECK-INST: th.vnmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a ae <unknown>
+
+th.vnmsub.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vnmsub.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 ac <unknown>
+
+th.vnmsub.vx v8, a0, v4
+# CHECK-INST: th.vnmsub.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 ae <unknown>
+
+th.vwmaccu.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vwmaccu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a f0 <unknown>
+
+th.vwmaccu.vv v8, v20, v4
+# CHECK-INST: th.vwmaccu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a f2 <unknown>
+
+th.vwmaccu.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwmaccu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 f0 <unknown>
+
+th.vwmaccu.vx v8, a0, v4
+# CHECK-INST: th.vwmaccu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 f2 <unknown>
+
+th.vwmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vwmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a f4 <unknown>
+
+th.vwmacc.vv v8, v20, v4
+# CHECK-INST: th.vwmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a f6 <unknown>
+
+th.vwmacc.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwmacc.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 f4 <unknown>
+
+th.vwmacc.vx v8, a0, v4
+# CHECK-INST: th.vwmacc.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 f6 <unknown>
+
+th.vwmaccsu.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vwmaccsu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a f8 <unknown>
+
+th.vwmaccsu.vv v8, v20, v4
+# CHECK-INST: th.vwmaccsu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xfa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 24 4a fa <unknown>
+
+th.vwmaccsu.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwmaccsu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 f8 <unknown>
+
+th.vwmaccsu.vx v8, a0, v4
+# CHECK-INST: th.vwmaccsu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xfa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 fa <unknown>
+
+th.vwmaccus.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwmaccus.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 fc <unknown>
+
+th.vwmaccus.vx v8, a0, v4
+# CHECK-INST: th.vwmaccus.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 64 45 fe <unknown>
+
+th.vwsmaccu.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vwsmaccu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a f0 <unknown>
+
+th.vwsmaccu.vv v8, v20, v4
+# CHECK-INST: th.vwsmaccu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a f2 <unknown>
+
+th.vwsmaccu.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwsmaccu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf0]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 f0 <unknown>
+
+th.vwsmaccu.vx v8, a0, v4
+# CHECK-INST: th.vwsmaccu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf2]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 f2 <unknown>
+
+th.vwsmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vwsmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a f4 <unknown>
+
+th.vwsmacc.vv v8, v20, v4
+# CHECK-INST: th.vwsmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a f6 <unknown>
+
+th.vwsmacc.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwsmacc.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf4]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 f4 <unknown>
+
+th.vwsmacc.vx v8, a0, v4
+# CHECK-INST: th.vwsmacc.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf6]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 f6 <unknown>
+
+th.vwsmaccsu.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vwsmaccsu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a f8 <unknown>
+
+th.vwsmaccsu.vv v8, v20, v4
+# CHECK-INST: th.vwsmaccsu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xfa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 04 4a fa <unknown>
+
+th.vwsmaccsu.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwsmaccsu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf8]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 f8 <unknown>
+
+th.vwsmaccsu.vx v8, a0, v4
+# CHECK-INST: th.vwsmaccsu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfa]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 fa <unknown>
+
+th.vwsmaccus.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vwsmaccus.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 fc <unknown>
+
+th.vwsmaccus.vx v8, a0, v4
+# CHECK-INST: th.vwsmaccus.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}}
+# CHECK-UNKNOWN: 57 44 45 fe <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/RISCV/xtheadvector/vector-insns.s b/llvm/test/MC/RISCV/xtheadvector/vector-insns.s
new file mode 100644
index 00000000000000..7682523f03e472
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/vector-insns.s
@@ -0,0 +1,6856 @@
+# Adapted from https://github.com/riscvarchive/riscv-binutils-gdb/blob/1aeeeab05f3c39e2bfc6e99384490d4c7f484ba0/gas/testsuite/gas/riscv/vector-insns.s
+# Golden value for this test: https://github.com/riscvarchive/riscv-binutils-gdb/blob/1aeeeab05f3c39e2bfc6e99384490d4c7f484ba0/gas/testsuite/gas/riscv/vector-insns.d
+# Generated using the script: https://gist.github.com/imkiva/05facf1a51ff8abfeeeea8fa7bc307ad#file-rvvtestgen-java
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+f,+a,+xtheadvector,+xtheadzvamo %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+th.vsetvl a0, a1, a2
+# CHECK-INST: th.vsetvl a0, a1, a2
+# CHECK-ENCODING: [0x57,0xf5,0xc5,0x80]
+
+th.vsetvli a0, a1, 0
+# CHECK-INST: th.vsetvli a0, a1, e8, m1, d1
+# CHECK-ENCODING: [0x57,0xf5,0x05,0x00]
+
+th.vsetvli a0, a1, 0x7ff
+# CHECK-INST: th.vsetvli a0, a1, 2047
+# CHECK-ENCODING: [0x57,0xf5,0xf5,0x7f]
+
+th.vsetvli a0, a1, e16,m2,d4
+# CHECK-INST: th.vsetvli a0, a1, e16, m2, d4
+# CHECK-ENCODING: [0x57,0xf5,0x55,0x04]
+
+th.vlb.v v4, (a0)
+# CHECK-INST: th.vlb.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x12]
+
+th.vlb.v v4, 0(a0)
+# CHECK-INST: th.vlb.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x12]
+
+th.vlb.v v4, (a0), v0.t
+# CHECK-INST: th.vlb.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x10]
+
+th.vlh.v v4, (a0)
+# CHECK-INST: th.vlh.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x12]
+
+th.vlh.v v4, 0(a0)
+# CHECK-INST: th.vlh.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x12]
+
+th.vlh.v v4, (a0), v0.t
+# CHECK-INST: th.vlh.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x10]
+
+th.vlw.v v4, (a0)
+# CHECK-INST: th.vlw.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x12]
+
+th.vlw.v v4, 0(a0)
+# CHECK-INST: th.vlw.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x12]
+
+th.vlw.v v4, (a0), v0.t
+# CHECK-INST: th.vlw.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x10]
+
+th.vlbu.v v4, (a0)
+# CHECK-INST: th.vlbu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x02]
+
+th.vlbu.v v4, 0(a0)
+# CHECK-INST: th.vlbu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x02]
+
+th.vlbu.v v4, (a0), v0.t
+# CHECK-INST: th.vlbu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x00]
+
+th.vlhu.v v4, (a0)
+# CHECK-INST: th.vlhu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x02]
+
+th.vlhu.v v4, 0(a0)
+# CHECK-INST: th.vlhu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x02]
+
+th.vlhu.v v4, (a0), v0.t
+# CHECK-INST: th.vlhu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x00]
+
+th.vlwu.v v4, (a0)
+# CHECK-INST: th.vlwu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x02]
+
+th.vlwu.v v4, 0(a0)
+# CHECK-INST: th.vlwu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x02]
+
+th.vlwu.v v4, (a0), v0.t
+# CHECK-INST: th.vlwu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x00]
+
+th.vle.v v4, (a0)
+# CHECK-INST: th.vle.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x02]
+
+th.vle.v v4, 0(a0)
+# CHECK-INST: th.vle.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x02]
+
+th.vle.v v4, (a0), v0.t
+# CHECK-INST: th.vle.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x00]
+
+th.vsb.v v4, (a0)
+# CHECK-INST: th.vsb.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x02]
+
+th.vsb.v v4, 0(a0)
+# CHECK-INST: th.vsb.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x02]
+
+th.vsb.v v4, (a0), v0.t
+# CHECK-INST: th.vsb.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0x00]
+
+th.vsh.v v4, (a0)
+# CHECK-INST: th.vsh.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x02]
+
+th.vsh.v v4, 0(a0)
+# CHECK-INST: th.vsh.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x02]
+
+th.vsh.v v4, (a0), v0.t
+# CHECK-INST: th.vsh.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0x00]
+
+th.vsw.v v4, (a0)
+# CHECK-INST: th.vsw.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x02]
+
+th.vsw.v v4, 0(a0)
+# CHECK-INST: th.vsw.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x02]
+
+th.vsw.v v4, (a0), v0.t
+# CHECK-INST: th.vsw.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0x00]
+
+th.vse.v v4, (a0)
+# CHECK-INST: th.vse.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x02]
+
+th.vse.v v4, 0(a0)
+# CHECK-INST: th.vse.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x02]
+
+th.vse.v v4, (a0), v0.t
+# CHECK-INST: th.vse.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0x00]
+
+th.vlsb.v v4, (a0), a1
+# CHECK-INST: th.vlsb.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x1a]
+
+th.vlsb.v v4, 0(a0), a1
+# CHECK-INST: th.vlsb.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x1a]
+
+th.vlsb.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsb.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x18]
+
+th.vlsh.v v4, (a0), a1
+# CHECK-INST: th.vlsh.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x1a]
+
+th.vlsh.v v4, 0(a0), a1
+# CHECK-INST: th.vlsh.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x1a]
+
+th.vlsh.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsh.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x18]
+
+th.vlsw.v v4, (a0), a1
+# CHECK-INST: th.vlsw.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x1a]
+
+th.vlsw.v v4, 0(a0), a1
+# CHECK-INST: th.vlsw.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x1a]
+
+th.vlsw.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsw.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x18]
+
+th.vlsbu.v v4, (a0), a1
+# CHECK-INST: th.vlsbu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x0a]
+
+th.vlsbu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsbu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x0a]
+
+th.vlsbu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsbu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x08]
+
+th.vlshu.v v4, (a0), a1
+# CHECK-INST: th.vlshu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x0a]
+
+th.vlshu.v v4, 0(a0), a1
+# CHECK-INST: th.vlshu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x0a]
+
+th.vlshu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlshu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x08]
+
+th.vlswu.v v4, (a0), a1
+# CHECK-INST: th.vlswu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x0a]
+
+th.vlswu.v v4, 0(a0), a1
+# CHECK-INST: th.vlswu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x0a]
+
+th.vlswu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlswu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x08]
+
+th.vlse.v v4, (a0), a1
+# CHECK-INST: th.vlse.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x0a]
+
+th.vlse.v v4, 0(a0), a1
+# CHECK-INST: th.vlse.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x0a]
+
+th.vlse.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlse.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x08]
+
+th.vssb.v v4, (a0), a1
+# CHECK-INST: th.vssb.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x0a]
+
+th.vssb.v v4, 0(a0), a1
+# CHECK-INST: th.vssb.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x0a]
+
+th.vssb.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssb.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x08]
+
+th.vssh.v v4, (a0), a1
+# CHECK-INST: th.vssh.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x0a]
+
+th.vssh.v v4, 0(a0), a1
+# CHECK-INST: th.vssh.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x0a]
+
+th.vssh.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssh.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x08]
+
+th.vssw.v v4, (a0), a1
+# CHECK-INST: th.vssw.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x0a]
+
+th.vssw.v v4, 0(a0), a1
+# CHECK-INST: th.vssw.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x0a]
+
+th.vssw.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssw.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x08]
+
+th.vsse.v v4, (a0), a1
+# CHECK-INST: th.vsse.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x0a]
+
+th.vsse.v v4, 0(a0), a1
+# CHECK-INST: th.vsse.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x0a]
+
+th.vsse.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vsse.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x08]
+
+th.vlxb.v v4, (a0), v12
+# CHECK-INST: th.vlxb.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x1e]
+
+th.vlxb.v v4, 0(a0), v12
+# CHECK-INST: th.vlxb.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x1e]
+
+th.vlxb.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxb.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x1c]
+
+th.vlxh.v v4, (a0), v12
+# CHECK-INST: th.vlxh.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x1e]
+
+th.vlxh.v v4, 0(a0), v12
+# CHECK-INST: th.vlxh.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x1e]
+
+th.vlxh.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxh.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x1c]
+
+th.vlxw.v v4, (a0), v12
+# CHECK-INST: th.vlxw.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x1e]
+
+th.vlxw.v v4, 0(a0), v12
+# CHECK-INST: th.vlxw.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x1e]
+
+th.vlxw.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxw.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x1c]
+
+th.vlxbu.v v4, (a0), v12
+# CHECK-INST: th.vlxbu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x0e]
+
+th.vlxbu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxbu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x0e]
+
+th.vlxbu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxbu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x0c]
+
+th.vlxhu.v v4, (a0), v12
+# CHECK-INST: th.vlxhu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x0e]
+
+th.vlxhu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxhu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x0e]
+
+th.vlxhu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxhu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x0c]
+
+th.vlxwu.v v4, (a0), v12
+# CHECK-INST: th.vlxwu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x0e]
+
+th.vlxwu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxwu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x0e]
+
+th.vlxwu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxwu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x0c]
+
+th.vlxe.v v4, (a0), v12
+# CHECK-INST: th.vlxe.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x0e]
+
+th.vlxe.v v4, 0(a0), v12
+# CHECK-INST: th.vlxe.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x0e]
+
+th.vlxe.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxe.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x0c]
+
+th.vsxb.v v4, (a0), v12
+# CHECK-INST: th.vsxb.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x0e]
+
+th.vsxb.v v4, 0(a0), v12
+# CHECK-INST: th.vsxb.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x0e]
+
+th.vsxb.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxb.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x0c]
+
+th.vsxh.v v4, (a0), v12
+# CHECK-INST: th.vsxh.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x0e]
+
+th.vsxh.v v4, 0(a0), v12
+# CHECK-INST: th.vsxh.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x0e]
+
+th.vsxh.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxh.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x0c]
+
+th.vsxw.v v4, (a0), v12
+# CHECK-INST: th.vsxw.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x0e]
+
+th.vsxw.v v4, 0(a0), v12
+# CHECK-INST: th.vsxw.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x0e]
+
+th.vsxw.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxw.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x0c]
+
+th.vsxe.v v4, (a0), v12
+# CHECK-INST: th.vsxe.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x0e]
+
+th.vsxe.v v4, 0(a0), v12
+# CHECK-INST: th.vsxe.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x0e]
+
+th.vsxe.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxe.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x0c]
+
+th.vsuxb.v v4, (a0), v12
+# CHECK-INST: th.vsuxb.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x1e]
+
+th.vsuxb.v v4, 0(a0), v12
+# CHECK-INST: th.vsuxb.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x1e]
+
+th.vsuxb.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsuxb.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x1c]
+
+th.vsuxh.v v4, (a0), v12
+# CHECK-INST: th.vsuxh.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x1e]
+
+th.vsuxh.v v4, 0(a0), v12
+# CHECK-INST: th.vsuxh.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x1e]
+
+th.vsuxh.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsuxh.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x1c]
+
+th.vsuxw.v v4, (a0), v12
+# CHECK-INST: th.vsuxw.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x1e]
+
+th.vsuxw.v v4, 0(a0), v12
+# CHECK-INST: th.vsuxw.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x1e]
+
+th.vsuxw.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsuxw.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x1c]
+
+th.vsuxe.v v4, (a0), v12
+# CHECK-INST: th.vsuxe.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x1e]
+
+th.vsuxe.v v4, 0(a0), v12
+# CHECK-INST: th.vsuxe.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x1e]
+
+th.vsuxe.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsuxe.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x1c]
+
+th.vlbff.v v4, (a0)
+# CHECK-INST: th.vlbff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x13]
+
+th.vlbff.v v4, 0(a0)
+# CHECK-INST: th.vlbff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x13]
+
+th.vlbff.v v4, (a0), v0.t
+# CHECK-INST: th.vlbff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x11]
+
+th.vlhff.v v4, (a0)
+# CHECK-INST: th.vlhff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x13]
+
+th.vlhff.v v4, 0(a0)
+# CHECK-INST: th.vlhff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x13]
+
+th.vlhff.v v4, (a0), v0.t
+# CHECK-INST: th.vlhff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x11]
+
+th.vlwff.v v4, (a0)
+# CHECK-INST: th.vlwff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x13]
+
+th.vlwff.v v4, 0(a0)
+# CHECK-INST: th.vlwff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x13]
+
+th.vlwff.v v4, (a0), v0.t
+# CHECK-INST: th.vlwff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x11]
+
+th.vlbuff.v v4, (a0)
+# CHECK-INST: th.vlbuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x03]
+
+th.vlbuff.v v4, 0(a0)
+# CHECK-INST: th.vlbuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x03]
+
+th.vlbuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlbuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x01]
+
+th.vlhuff.v v4, (a0)
+# CHECK-INST: th.vlhuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x03]
+
+th.vlhuff.v v4, 0(a0)
+# CHECK-INST: th.vlhuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x03]
+
+th.vlhuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlhuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x01]
+
+th.vlwuff.v v4, (a0)
+# CHECK-INST: th.vlwuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x03]
+
+th.vlwuff.v v4, 0(a0)
+# CHECK-INST: th.vlwuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x03]
+
+th.vlwuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlwuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x01]
+
+th.vleff.v v4, (a0)
+# CHECK-INST: th.vleff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x03]
+
+th.vleff.v v4, 0(a0)
+# CHECK-INST: th.vleff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x03]
+
+th.vleff.v v4, (a0), v0.t
+# CHECK-INST: th.vleff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x01]
+
+th.vlseg2b.v v4, (a0)
+# CHECK-INST: th.vlseg2b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x32]
+
+th.vlseg2b.v v4, 0(a0)
+# CHECK-INST: th.vlseg2b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x32]
+
+th.vlseg2b.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x30]
+
+th.vlseg2h.v v4, (a0)
+# CHECK-INST: th.vlseg2h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x32]
+
+th.vlseg2h.v v4, 0(a0)
+# CHECK-INST: th.vlseg2h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x32]
+
+th.vlseg2h.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x30]
+
+th.vlseg2w.v v4, (a0)
+# CHECK-INST: th.vlseg2w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x32]
+
+th.vlseg2w.v v4, 0(a0)
+# CHECK-INST: th.vlseg2w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x32]
+
+th.vlseg2w.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x30]
+
+th.vlseg2bu.v v4, (a0)
+# CHECK-INST: th.vlseg2bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x22]
+
+th.vlseg2bu.v v4, 0(a0)
+# CHECK-INST: th.vlseg2bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x22]
+
+th.vlseg2bu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2bu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x20]
+
+th.vlseg2hu.v v4, (a0)
+# CHECK-INST: th.vlseg2hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x22]
+
+th.vlseg2hu.v v4, 0(a0)
+# CHECK-INST: th.vlseg2hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x22]
+
+th.vlseg2hu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2hu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x20]
+
+th.vlseg2wu.v v4, (a0)
+# CHECK-INST: th.vlseg2wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x22]
+
+th.vlseg2wu.v v4, 0(a0)
+# CHECK-INST: th.vlseg2wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x22]
+
+th.vlseg2wu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2wu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x20]
+
+th.vlseg2e.v v4, (a0)
+# CHECK-INST: th.vlseg2e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x22]
+
+th.vlseg2e.v v4, 0(a0)
+# CHECK-INST: th.vlseg2e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x22]
+
+th.vlseg2e.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x20]
+
+th.vsseg2b.v v4, (a0)
+# CHECK-INST: th.vsseg2b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x22]
+
+th.vsseg2b.v v4, 0(a0)
+# CHECK-INST: th.vsseg2b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x22]
+
+th.vsseg2b.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg2b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0x20]
+
+th.vsseg2h.v v4, (a0)
+# CHECK-INST: th.vsseg2h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x22]
+
+th.vsseg2h.v v4, 0(a0)
+# CHECK-INST: th.vsseg2h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x22]
+
+th.vsseg2h.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg2h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0x20]
+
+th.vsseg2w.v v4, (a0)
+# CHECK-INST: th.vsseg2w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x22]
+
+th.vsseg2w.v v4, 0(a0)
+# CHECK-INST: th.vsseg2w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x22]
+
+th.vsseg2w.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg2w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0x20]
+
+th.vsseg2e.v v4, (a0)
+# CHECK-INST: th.vsseg2e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x22]
+
+th.vsseg2e.v v4, 0(a0)
+# CHECK-INST: th.vsseg2e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x22]
+
+th.vsseg2e.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg2e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0x20]
+
+th.vlseg3b.v v4, (a0)
+# CHECK-INST: th.vlseg3b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x52]
+
+th.vlseg3b.v v4, 0(a0)
+# CHECK-INST: th.vlseg3b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x52]
+
+th.vlseg3b.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x50]
+
+th.vlseg3h.v v4, (a0)
+# CHECK-INST: th.vlseg3h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x52]
+
+th.vlseg3h.v v4, 0(a0)
+# CHECK-INST: th.vlseg3h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x52]
+
+th.vlseg3h.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x50]
+
+th.vlseg3w.v v4, (a0)
+# CHECK-INST: th.vlseg3w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x52]
+
+th.vlseg3w.v v4, 0(a0)
+# CHECK-INST: th.vlseg3w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x52]
+
+th.vlseg3w.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x50]
+
+th.vlseg3bu.v v4, (a0)
+# CHECK-INST: th.vlseg3bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x42]
+
+th.vlseg3bu.v v4, 0(a0)
+# CHECK-INST: th.vlseg3bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x42]
+
+th.vlseg3bu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3bu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x40]
+
+th.vlseg3hu.v v4, (a0)
+# CHECK-INST: th.vlseg3hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x42]
+
+th.vlseg3hu.v v4, 0(a0)
+# CHECK-INST: th.vlseg3hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x42]
+
+th.vlseg3hu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3hu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x40]
+
+th.vlseg3wu.v v4, (a0)
+# CHECK-INST: th.vlseg3wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x42]
+
+th.vlseg3wu.v v4, 0(a0)
+# CHECK-INST: th.vlseg3wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x42]
+
+th.vlseg3wu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3wu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x40]
+
+th.vlseg3e.v v4, (a0)
+# CHECK-INST: th.vlseg3e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x42]
+
+th.vlseg3e.v v4, 0(a0)
+# CHECK-INST: th.vlseg3e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x42]
+
+th.vlseg3e.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x40]
+
+th.vsseg3b.v v4, (a0)
+# CHECK-INST: th.vsseg3b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x42]
+
+th.vsseg3b.v v4, 0(a0)
+# CHECK-INST: th.vsseg3b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x42]
+
+th.vsseg3b.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg3b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0x40]
+
+th.vsseg3h.v v4, (a0)
+# CHECK-INST: th.vsseg3h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x42]
+
+th.vsseg3h.v v4, 0(a0)
+# CHECK-INST: th.vsseg3h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x42]
+
+th.vsseg3h.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg3h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0x40]
+
+th.vsseg3w.v v4, (a0)
+# CHECK-INST: th.vsseg3w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x42]
+
+th.vsseg3w.v v4, 0(a0)
+# CHECK-INST: th.vsseg3w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x42]
+
+th.vsseg3w.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg3w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0x40]
+
+th.vsseg3e.v v4, (a0)
+# CHECK-INST: th.vsseg3e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x42]
+
+th.vsseg3e.v v4, 0(a0)
+# CHECK-INST: th.vsseg3e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x42]
+
+th.vsseg3e.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg3e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0x40]
+
+th.vlseg4b.v v4, (a0)
+# CHECK-INST: th.vlseg4b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x72]
+
+th.vlseg4b.v v4, 0(a0)
+# CHECK-INST: th.vlseg4b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x72]
+
+th.vlseg4b.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x70]
+
+th.vlseg4h.v v4, (a0)
+# CHECK-INST: th.vlseg4h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x72]
+
+th.vlseg4h.v v4, 0(a0)
+# CHECK-INST: th.vlseg4h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x72]
+
+th.vlseg4h.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x70]
+
+th.vlseg4w.v v4, (a0)
+# CHECK-INST: th.vlseg4w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x72]
+
+th.vlseg4w.v v4, 0(a0)
+# CHECK-INST: th.vlseg4w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x72]
+
+th.vlseg4w.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x70]
+
+th.vlseg4bu.v v4, (a0)
+# CHECK-INST: th.vlseg4bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x62]
+
+th.vlseg4bu.v v4, 0(a0)
+# CHECK-INST: th.vlseg4bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x62]
+
+th.vlseg4bu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4bu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x60]
+
+th.vlseg4hu.v v4, (a0)
+# CHECK-INST: th.vlseg4hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x62]
+
+th.vlseg4hu.v v4, 0(a0)
+# CHECK-INST: th.vlseg4hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x62]
+
+th.vlseg4hu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4hu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x60]
+
+th.vlseg4wu.v v4, (a0)
+# CHECK-INST: th.vlseg4wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x62]
+
+th.vlseg4wu.v v4, 0(a0)
+# CHECK-INST: th.vlseg4wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x62]
+
+th.vlseg4wu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4wu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x60]
+
+th.vlseg4e.v v4, (a0)
+# CHECK-INST: th.vlseg4e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x62]
+
+th.vlseg4e.v v4, 0(a0)
+# CHECK-INST: th.vlseg4e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x62]
+
+th.vlseg4e.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x60]
+
+th.vsseg4b.v v4, (a0)
+# CHECK-INST: th.vsseg4b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x62]
+
+th.vsseg4b.v v4, 0(a0)
+# CHECK-INST: th.vsseg4b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x62]
+
+th.vsseg4b.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg4b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0x60]
+
+th.vsseg4h.v v4, (a0)
+# CHECK-INST: th.vsseg4h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x62]
+
+th.vsseg4h.v v4, 0(a0)
+# CHECK-INST: th.vsseg4h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x62]
+
+th.vsseg4h.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg4h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0x60]
+
+th.vsseg4w.v v4, (a0)
+# CHECK-INST: th.vsseg4w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x62]
+
+th.vsseg4w.v v4, 0(a0)
+# CHECK-INST: th.vsseg4w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x62]
+
+th.vsseg4w.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg4w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0x60]
+
+th.vsseg4e.v v4, (a0)
+# CHECK-INST: th.vsseg4e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x62]
+
+th.vsseg4e.v v4, 0(a0)
+# CHECK-INST: th.vsseg4e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x62]
+
+th.vsseg4e.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg4e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0x60]
+
+th.vlseg5b.v v4, (a0)
+# CHECK-INST: th.vlseg5b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x92]
+
+th.vlseg5b.v v4, 0(a0)
+# CHECK-INST: th.vlseg5b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x92]
+
+th.vlseg5b.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x90]
+
+th.vlseg5h.v v4, (a0)
+# CHECK-INST: th.vlseg5h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x92]
+
+th.vlseg5h.v v4, 0(a0)
+# CHECK-INST: th.vlseg5h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x92]
+
+th.vlseg5h.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x90]
+
+th.vlseg5w.v v4, (a0)
+# CHECK-INST: th.vlseg5w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x92]
+
+th.vlseg5w.v v4, 0(a0)
+# CHECK-INST: th.vlseg5w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x92]
+
+th.vlseg5w.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x90]
+
+th.vlseg5bu.v v4, (a0)
+# CHECK-INST: th.vlseg5bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x82]
+
+th.vlseg5bu.v v4, 0(a0)
+# CHECK-INST: th.vlseg5bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x82]
+
+th.vlseg5bu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5bu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x80]
+
+th.vlseg5hu.v v4, (a0)
+# CHECK-INST: th.vlseg5hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x82]
+
+th.vlseg5hu.v v4, 0(a0)
+# CHECK-INST: th.vlseg5hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x82]
+
+th.vlseg5hu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5hu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x80]
+
+th.vlseg5wu.v v4, (a0)
+# CHECK-INST: th.vlseg5wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x82]
+
+th.vlseg5wu.v v4, 0(a0)
+# CHECK-INST: th.vlseg5wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x82]
+
+th.vlseg5wu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5wu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x80]
+
+th.vlseg5e.v v4, (a0)
+# CHECK-INST: th.vlseg5e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x82]
+
+th.vlseg5e.v v4, 0(a0)
+# CHECK-INST: th.vlseg5e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x82]
+
+th.vlseg5e.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x80]
+
+th.vsseg5b.v v4, (a0)
+# CHECK-INST: th.vsseg5b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x82]
+
+th.vsseg5b.v v4, 0(a0)
+# CHECK-INST: th.vsseg5b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0x82]
+
+th.vsseg5b.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg5b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0x80]
+
+th.vsseg5h.v v4, (a0)
+# CHECK-INST: th.vsseg5h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x82]
+
+th.vsseg5h.v v4, 0(a0)
+# CHECK-INST: th.vsseg5h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0x82]
+
+th.vsseg5h.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg5h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0x80]
+
+th.vsseg5w.v v4, (a0)
+# CHECK-INST: th.vsseg5w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x82]
+
+th.vsseg5w.v v4, 0(a0)
+# CHECK-INST: th.vsseg5w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0x82]
+
+th.vsseg5w.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg5w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0x80]
+
+th.vsseg5e.v v4, (a0)
+# CHECK-INST: th.vsseg5e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x82]
+
+th.vsseg5e.v v4, 0(a0)
+# CHECK-INST: th.vsseg5e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0x82]
+
+th.vsseg5e.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg5e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0x80]
+
+th.vlseg6b.v v4, (a0)
+# CHECK-INST: th.vlseg6b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xb2]
+
+th.vlseg6b.v v4, 0(a0)
+# CHECK-INST: th.vlseg6b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xb2]
+
+th.vlseg6b.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xb0]
+
+th.vlseg6h.v v4, (a0)
+# CHECK-INST: th.vlseg6h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xb2]
+
+th.vlseg6h.v v4, 0(a0)
+# CHECK-INST: th.vlseg6h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xb2]
+
+th.vlseg6h.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xb0]
+
+th.vlseg6w.v v4, (a0)
+# CHECK-INST: th.vlseg6w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xb2]
+
+th.vlseg6w.v v4, 0(a0)
+# CHECK-INST: th.vlseg6w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xb2]
+
+th.vlseg6w.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xb0]
+
+th.vlseg6bu.v v4, (a0)
+# CHECK-INST: th.vlseg6bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xa2]
+
+th.vlseg6bu.v v4, 0(a0)
+# CHECK-INST: th.vlseg6bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xa2]
+
+th.vlseg6bu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6bu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xa0]
+
+th.vlseg6hu.v v4, (a0)
+# CHECK-INST: th.vlseg6hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xa2]
+
+th.vlseg6hu.v v4, 0(a0)
+# CHECK-INST: th.vlseg6hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xa2]
+
+th.vlseg6hu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6hu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xa0]
+
+th.vlseg6wu.v v4, (a0)
+# CHECK-INST: th.vlseg6wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xa2]
+
+th.vlseg6wu.v v4, 0(a0)
+# CHECK-INST: th.vlseg6wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xa2]
+
+th.vlseg6wu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6wu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xa0]
+
+th.vlseg6e.v v4, (a0)
+# CHECK-INST: th.vlseg6e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xa2]
+
+th.vlseg6e.v v4, 0(a0)
+# CHECK-INST: th.vlseg6e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xa2]
+
+th.vlseg6e.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0xa0]
+
+th.vsseg6b.v v4, (a0)
+# CHECK-INST: th.vsseg6b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0xa2]
+
+th.vsseg6b.v v4, 0(a0)
+# CHECK-INST: th.vsseg6b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0xa2]
+
+th.vsseg6b.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg6b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0xa0]
+
+th.vsseg6h.v v4, (a0)
+# CHECK-INST: th.vsseg6h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0xa2]
+
+th.vsseg6h.v v4, 0(a0)
+# CHECK-INST: th.vsseg6h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0xa2]
+
+th.vsseg6h.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg6h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0xa0]
+
+th.vsseg6w.v v4, (a0)
+# CHECK-INST: th.vsseg6w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0xa2]
+
+th.vsseg6w.v v4, 0(a0)
+# CHECK-INST: th.vsseg6w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0xa2]
+
+th.vsseg6w.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg6w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0xa0]
+
+th.vsseg6e.v v4, (a0)
+# CHECK-INST: th.vsseg6e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0xa2]
+
+th.vsseg6e.v v4, 0(a0)
+# CHECK-INST: th.vsseg6e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0xa2]
+
+th.vsseg6e.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg6e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0xa0]
+
+th.vlseg7b.v v4, (a0)
+# CHECK-INST: th.vlseg7b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xd2]
+
+th.vlseg7b.v v4, 0(a0)
+# CHECK-INST: th.vlseg7b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xd2]
+
+th.vlseg7b.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xd0]
+
+th.vlseg7h.v v4, (a0)
+# CHECK-INST: th.vlseg7h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xd2]
+
+th.vlseg7h.v v4, 0(a0)
+# CHECK-INST: th.vlseg7h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xd2]
+
+th.vlseg7h.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xd0]
+
+th.vlseg7w.v v4, (a0)
+# CHECK-INST: th.vlseg7w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xd2]
+
+th.vlseg7w.v v4, 0(a0)
+# CHECK-INST: th.vlseg7w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xd2]
+
+th.vlseg7w.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xd0]
+
+th.vlseg7bu.v v4, (a0)
+# CHECK-INST: th.vlseg7bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xc2]
+
+th.vlseg7bu.v v4, 0(a0)
+# CHECK-INST: th.vlseg7bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xc2]
+
+th.vlseg7bu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7bu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xc0]
+
+th.vlseg7hu.v v4, (a0)
+# CHECK-INST: th.vlseg7hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xc2]
+
+th.vlseg7hu.v v4, 0(a0)
+# CHECK-INST: th.vlseg7hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xc2]
+
+th.vlseg7hu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7hu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xc0]
+
+th.vlseg7wu.v v4, (a0)
+# CHECK-INST: th.vlseg7wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xc2]
+
+th.vlseg7wu.v v4, 0(a0)
+# CHECK-INST: th.vlseg7wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xc2]
+
+th.vlseg7wu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7wu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xc0]
+
+th.vlseg7e.v v4, (a0)
+# CHECK-INST: th.vlseg7e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xc2]
+
+th.vlseg7e.v v4, 0(a0)
+# CHECK-INST: th.vlseg7e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xc2]
+
+th.vlseg7e.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0xc0]
+
+th.vsseg7b.v v4, (a0)
+# CHECK-INST: th.vsseg7b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0xc2]
+
+th.vsseg7b.v v4, 0(a0)
+# CHECK-INST: th.vsseg7b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0xc2]
+
+th.vsseg7b.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg7b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0xc0]
+
+th.vsseg7h.v v4, (a0)
+# CHECK-INST: th.vsseg7h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0xc2]
+
+th.vsseg7h.v v4, 0(a0)
+# CHECK-INST: th.vsseg7h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0xc2]
+
+th.vsseg7h.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg7h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0xc0]
+
+th.vsseg7w.v v4, (a0)
+# CHECK-INST: th.vsseg7w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0xc2]
+
+th.vsseg7w.v v4, 0(a0)
+# CHECK-INST: th.vsseg7w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0xc2]
+
+th.vsseg7w.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg7w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0xc0]
+
+th.vsseg7e.v v4, (a0)
+# CHECK-INST: th.vsseg7e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0xc2]
+
+th.vsseg7e.v v4, 0(a0)
+# CHECK-INST: th.vsseg7e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0xc2]
+
+th.vsseg7e.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg7e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0xc0]
+
+th.vlseg8b.v v4, (a0)
+# CHECK-INST: th.vlseg8b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xf2]
+
+th.vlseg8b.v v4, 0(a0)
+# CHECK-INST: th.vlseg8b.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xf2]
+
+th.vlseg8b.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xf0]
+
+th.vlseg8h.v v4, (a0)
+# CHECK-INST: th.vlseg8h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xf2]
+
+th.vlseg8h.v v4, 0(a0)
+# CHECK-INST: th.vlseg8h.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xf2]
+
+th.vlseg8h.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xf0]
+
+th.vlseg8w.v v4, (a0)
+# CHECK-INST: th.vlseg8w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xf2]
+
+th.vlseg8w.v v4, 0(a0)
+# CHECK-INST: th.vlseg8w.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xf2]
+
+th.vlseg8w.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xf0]
+
+th.vlseg8bu.v v4, (a0)
+# CHECK-INST: th.vlseg8bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xe2]
+
+th.vlseg8bu.v v4, 0(a0)
+# CHECK-INST: th.vlseg8bu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xe2]
+
+th.vlseg8bu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8bu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xe0]
+
+th.vlseg8hu.v v4, (a0)
+# CHECK-INST: th.vlseg8hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xe2]
+
+th.vlseg8hu.v v4, 0(a0)
+# CHECK-INST: th.vlseg8hu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xe2]
+
+th.vlseg8hu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8hu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xe0]
+
+th.vlseg8wu.v v4, (a0)
+# CHECK-INST: th.vlseg8wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xe2]
+
+th.vlseg8wu.v v4, 0(a0)
+# CHECK-INST: th.vlseg8wu.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xe2]
+
+th.vlseg8wu.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8wu.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xe0]
+
+th.vlseg8e.v v4, (a0)
+# CHECK-INST: th.vlseg8e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xe2]
+
+th.vlseg8e.v v4, 0(a0)
+# CHECK-INST: th.vlseg8e.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xe2]
+
+th.vlseg8e.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0xe0]
+
+th.vsseg8b.v v4, (a0)
+# CHECK-INST: th.vsseg8b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0xe2]
+
+th.vsseg8b.v v4, 0(a0)
+# CHECK-INST: th.vsseg8b.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x02,0x05,0xe2]
+
+th.vsseg8b.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg8b.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x02,0x05,0xe0]
+
+th.vsseg8h.v v4, (a0)
+# CHECK-INST: th.vsseg8h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0xe2]
+
+th.vsseg8h.v v4, 0(a0)
+# CHECK-INST: th.vsseg8h.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x52,0x05,0xe2]
+
+th.vsseg8h.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg8h.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x52,0x05,0xe0]
+
+th.vsseg8w.v v4, (a0)
+# CHECK-INST: th.vsseg8w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0xe2]
+
+th.vsseg8w.v v4, 0(a0)
+# CHECK-INST: th.vsseg8w.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x62,0x05,0xe2]
+
+th.vsseg8w.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg8w.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x62,0x05,0xe0]
+
+th.vsseg8e.v v4, (a0)
+# CHECK-INST: th.vsseg8e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0xe2]
+
+th.vsseg8e.v v4, 0(a0)
+# CHECK-INST: th.vsseg8e.v v4, (a0)
+# CHECK-ENCODING: [0x27,0x72,0x05,0xe2]
+
+th.vsseg8e.v v4, (a0), v0.t
+# CHECK-INST: th.vsseg8e.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x72,0x05,0xe0]
+
+th.vlsseg2b.v v4, (a0), a1
+# CHECK-INST: th.vlsseg2b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x3a]
+
+th.vlsseg2b.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg2b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x3a]
+
+th.vlsseg2b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x38]
+
+th.vlsseg2h.v v4, (a0), a1
+# CHECK-INST: th.vlsseg2h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x3a]
+
+th.vlsseg2h.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg2h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x3a]
+
+th.vlsseg2h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x38]
+
+th.vlsseg2w.v v4, (a0), a1
+# CHECK-INST: th.vlsseg2w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x3a]
+
+th.vlsseg2w.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg2w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x3a]
+
+th.vlsseg2w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x38]
+
+th.vlsseg2bu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg2bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x2a]
+
+th.vlsseg2bu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg2bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x2a]
+
+th.vlsseg2bu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2bu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x28]
+
+th.vlsseg2hu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg2hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x2a]
+
+th.vlsseg2hu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg2hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x2a]
+
+th.vlsseg2hu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2hu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x28]
+
+th.vlsseg2wu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg2wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x2a]
+
+th.vlsseg2wu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg2wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x2a]
+
+th.vlsseg2wu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2wu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x28]
+
+th.vlsseg2e.v v4, (a0), a1
+# CHECK-INST: th.vlsseg2e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x2a]
+
+th.vlsseg2e.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg2e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x2a]
+
+th.vlsseg2e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg2e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x28]
+
+th.vssseg2b.v v4, (a0), a1
+# CHECK-INST: th.vssseg2b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x2a]
+
+th.vssseg2b.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg2b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x2a]
+
+th.vssseg2b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x28]
+
+th.vssseg2h.v v4, (a0), a1
+# CHECK-INST: th.vssseg2h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x2a]
+
+th.vssseg2h.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg2h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x2a]
+
+th.vssseg2h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x28]
+
+th.vssseg2w.v v4, (a0), a1
+# CHECK-INST: th.vssseg2w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x2a]
+
+th.vssseg2w.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg2w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x2a]
+
+th.vssseg2w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x28]
+
+th.vssseg2e.v v4, (a0), a1
+# CHECK-INST: th.vssseg2e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x2a]
+
+th.vssseg2e.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg2e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x2a]
+
+th.vssseg2e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg2e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x28]
+
+th.vlsseg3b.v v4, (a0), a1
+# CHECK-INST: th.vlsseg3b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x5a]
+
+th.vlsseg3b.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg3b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x5a]
+
+th.vlsseg3b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x58]
+
+th.vlsseg3h.v v4, (a0), a1
+# CHECK-INST: th.vlsseg3h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x5a]
+
+th.vlsseg3h.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg3h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x5a]
+
+th.vlsseg3h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x58]
+
+th.vlsseg3w.v v4, (a0), a1
+# CHECK-INST: th.vlsseg3w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x5a]
+
+th.vlsseg3w.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg3w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x5a]
+
+th.vlsseg3w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x58]
+
+th.vlsseg3bu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg3bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x4a]
+
+th.vlsseg3bu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg3bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x4a]
+
+th.vlsseg3bu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3bu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x48]
+
+th.vlsseg3hu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg3hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x4a]
+
+th.vlsseg3hu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg3hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x4a]
+
+th.vlsseg3hu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3hu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x48]
+
+th.vlsseg3wu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg3wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x4a]
+
+th.vlsseg3wu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg3wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x4a]
+
+th.vlsseg3wu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3wu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x48]
+
+th.vlsseg3e.v v4, (a0), a1
+# CHECK-INST: th.vlsseg3e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x4a]
+
+th.vlsseg3e.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg3e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x4a]
+
+th.vlsseg3e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg3e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x48]
+
+th.vssseg3b.v v4, (a0), a1
+# CHECK-INST: th.vssseg3b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x4a]
+
+th.vssseg3b.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg3b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x4a]
+
+th.vssseg3b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x48]
+
+th.vssseg3h.v v4, (a0), a1
+# CHECK-INST: th.vssseg3h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x4a]
+
+th.vssseg3h.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg3h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x4a]
+
+th.vssseg3h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x48]
+
+th.vssseg3w.v v4, (a0), a1
+# CHECK-INST: th.vssseg3w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x4a]
+
+th.vssseg3w.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg3w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x4a]
+
+th.vssseg3w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x48]
+
+th.vssseg3e.v v4, (a0), a1
+# CHECK-INST: th.vssseg3e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x4a]
+
+th.vssseg3e.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg3e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x4a]
+
+th.vssseg3e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg3e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x48]
+
+th.vlsseg4b.v v4, (a0), a1
+# CHECK-INST: th.vlsseg4b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x7a]
+
+th.vlsseg4b.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg4b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x7a]
+
+th.vlsseg4b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x78]
+
+th.vlsseg4h.v v4, (a0), a1
+# CHECK-INST: th.vlsseg4h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x7a]
+
+th.vlsseg4h.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg4h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x7a]
+
+th.vlsseg4h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x78]
+
+th.vlsseg4w.v v4, (a0), a1
+# CHECK-INST: th.vlsseg4w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x7a]
+
+th.vlsseg4w.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg4w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x7a]
+
+th.vlsseg4w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x78]
+
+th.vlsseg4bu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg4bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x6a]
+
+th.vlsseg4bu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg4bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x6a]
+
+th.vlsseg4bu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4bu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x68]
+
+th.vlsseg4hu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg4hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x6a]
+
+th.vlsseg4hu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg4hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x6a]
+
+th.vlsseg4hu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4hu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x68]
+
+th.vlsseg4wu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg4wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x6a]
+
+th.vlsseg4wu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg4wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x6a]
+
+th.vlsseg4wu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4wu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x68]
+
+th.vlsseg4e.v v4, (a0), a1
+# CHECK-INST: th.vlsseg4e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x6a]
+
+th.vlsseg4e.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg4e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x6a]
+
+th.vlsseg4e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg4e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x68]
+
+th.vssseg4b.v v4, (a0), a1
+# CHECK-INST: th.vssseg4b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x6a]
+
+th.vssseg4b.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg4b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x6a]
+
+th.vssseg4b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x68]
+
+th.vssseg4h.v v4, (a0), a1
+# CHECK-INST: th.vssseg4h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x6a]
+
+th.vssseg4h.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg4h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x6a]
+
+th.vssseg4h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x68]
+
+th.vssseg4w.v v4, (a0), a1
+# CHECK-INST: th.vssseg4w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x6a]
+
+th.vssseg4w.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg4w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x6a]
+
+th.vssseg4w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x68]
+
+th.vssseg4e.v v4, (a0), a1
+# CHECK-INST: th.vssseg4e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x6a]
+
+th.vssseg4e.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg4e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x6a]
+
+th.vssseg4e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg4e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x68]
+
+th.vlsseg5b.v v4, (a0), a1
+# CHECK-INST: th.vlsseg5b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x9a]
+
+th.vlsseg5b.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg5b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x9a]
+
+th.vlsseg5b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x98]
+
+th.vlsseg5h.v v4, (a0), a1
+# CHECK-INST: th.vlsseg5h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x9a]
+
+th.vlsseg5h.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg5h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x9a]
+
+th.vlsseg5h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x98]
+
+th.vlsseg5w.v v4, (a0), a1
+# CHECK-INST: th.vlsseg5w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x9a]
+
+th.vlsseg5w.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg5w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x9a]
+
+th.vlsseg5w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x98]
+
+th.vlsseg5bu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg5bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x8a]
+
+th.vlsseg5bu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg5bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x8a]
+
+th.vlsseg5bu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5bu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0x88]
+
+th.vlsseg5hu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg5hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x8a]
+
+th.vlsseg5hu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg5hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x8a]
+
+th.vlsseg5hu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5hu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0x88]
+
+th.vlsseg5wu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg5wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x8a]
+
+th.vlsseg5wu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg5wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x8a]
+
+th.vlsseg5wu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5wu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0x88]
+
+th.vlsseg5e.v v4, (a0), a1
+# CHECK-INST: th.vlsseg5e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x8a]
+
+th.vlsseg5e.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg5e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x8a]
+
+th.vlsseg5e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg5e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0x88]
+
+th.vssseg5b.v v4, (a0), a1
+# CHECK-INST: th.vssseg5b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x8a]
+
+th.vssseg5b.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg5b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x8a]
+
+th.vssseg5b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0x88]
+
+th.vssseg5h.v v4, (a0), a1
+# CHECK-INST: th.vssseg5h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x8a]
+
+th.vssseg5h.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg5h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x8a]
+
+th.vssseg5h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0x88]
+
+th.vssseg5w.v v4, (a0), a1
+# CHECK-INST: th.vssseg5w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x8a]
+
+th.vssseg5w.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg5w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x8a]
+
+th.vssseg5w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0x88]
+
+th.vssseg5e.v v4, (a0), a1
+# CHECK-INST: th.vssseg5e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x8a]
+
+th.vssseg5e.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg5e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x8a]
+
+th.vssseg5e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg5e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0x88]
+
+th.vlsseg6b.v v4, (a0), a1
+# CHECK-INST: th.vlsseg6b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xba]
+
+th.vlsseg6b.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg6b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xba]
+
+th.vlsseg6b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xb8]
+
+th.vlsseg6h.v v4, (a0), a1
+# CHECK-INST: th.vlsseg6h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xba]
+
+th.vlsseg6h.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg6h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xba]
+
+th.vlsseg6h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xb8]
+
+th.vlsseg6w.v v4, (a0), a1
+# CHECK-INST: th.vlsseg6w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xba]
+
+th.vlsseg6w.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg6w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xba]
+
+th.vlsseg6w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xb8]
+
+th.vlsseg6bu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg6bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xaa]
+
+th.vlsseg6bu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg6bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xaa]
+
+th.vlsseg6bu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6bu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xa8]
+
+th.vlsseg6hu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg6hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xaa]
+
+th.vlsseg6hu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg6hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xaa]
+
+th.vlsseg6hu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6hu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xa8]
+
+th.vlsseg6wu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg6wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xaa]
+
+th.vlsseg6wu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg6wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xaa]
+
+th.vlsseg6wu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6wu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xa8]
+
+th.vlsseg6e.v v4, (a0), a1
+# CHECK-INST: th.vlsseg6e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xaa]
+
+th.vlsseg6e.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg6e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xaa]
+
+th.vlsseg6e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg6e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xa8]
+
+th.vssseg6b.v v4, (a0), a1
+# CHECK-INST: th.vssseg6b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xaa]
+
+th.vssseg6b.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg6b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xaa]
+
+th.vssseg6b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xa8]
+
+th.vssseg6h.v v4, (a0), a1
+# CHECK-INST: th.vssseg6h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xaa]
+
+th.vssseg6h.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg6h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xaa]
+
+th.vssseg6h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xa8]
+
+th.vssseg6w.v v4, (a0), a1
+# CHECK-INST: th.vssseg6w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xaa]
+
+th.vssseg6w.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg6w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xaa]
+
+th.vssseg6w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xa8]
+
+th.vssseg6e.v v4, (a0), a1
+# CHECK-INST: th.vssseg6e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xaa]
+
+th.vssseg6e.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg6e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xaa]
+
+th.vssseg6e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg6e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xa8]
+
+th.vlsseg7b.v v4, (a0), a1
+# CHECK-INST: th.vlsseg7b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xda]
+
+th.vlsseg7b.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg7b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xda]
+
+th.vlsseg7b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xd8]
+
+th.vlsseg7h.v v4, (a0), a1
+# CHECK-INST: th.vlsseg7h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xda]
+
+th.vlsseg7h.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg7h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xda]
+
+th.vlsseg7h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xd8]
+
+th.vlsseg7w.v v4, (a0), a1
+# CHECK-INST: th.vlsseg7w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xda]
+
+th.vlsseg7w.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg7w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xda]
+
+th.vlsseg7w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xd8]
+
+th.vlsseg7bu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg7bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xca]
+
+th.vlsseg7bu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg7bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xca]
+
+th.vlsseg7bu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7bu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xc8]
+
+th.vlsseg7hu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg7hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xca]
+
+th.vlsseg7hu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg7hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xca]
+
+th.vlsseg7hu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7hu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xc8]
+
+th.vlsseg7wu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg7wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xca]
+
+th.vlsseg7wu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg7wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xca]
+
+th.vlsseg7wu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7wu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xc8]
+
+th.vlsseg7e.v v4, (a0), a1
+# CHECK-INST: th.vlsseg7e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xca]
+
+th.vlsseg7e.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg7e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xca]
+
+th.vlsseg7e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg7e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xc8]
+
+th.vssseg7b.v v4, (a0), a1
+# CHECK-INST: th.vssseg7b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xca]
+
+th.vssseg7b.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg7b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xca]
+
+th.vssseg7b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xc8]
+
+th.vssseg7h.v v4, (a0), a1
+# CHECK-INST: th.vssseg7h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xca]
+
+th.vssseg7h.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg7h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xca]
+
+th.vssseg7h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xc8]
+
+th.vssseg7w.v v4, (a0), a1
+# CHECK-INST: th.vssseg7w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xca]
+
+th.vssseg7w.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg7w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xca]
+
+th.vssseg7w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xc8]
+
+th.vssseg7e.v v4, (a0), a1
+# CHECK-INST: th.vssseg7e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xca]
+
+th.vssseg7e.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg7e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xca]
+
+th.vssseg7e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg7e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xc8]
+
+th.vlsseg8b.v v4, (a0), a1
+# CHECK-INST: th.vlsseg8b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xfa]
+
+th.vlsseg8b.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg8b.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xfa]
+
+th.vlsseg8b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xf8]
+
+th.vlsseg8h.v v4, (a0), a1
+# CHECK-INST: th.vlsseg8h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xfa]
+
+th.vlsseg8h.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg8h.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xfa]
+
+th.vlsseg8h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xf8]
+
+th.vlsseg8w.v v4, (a0), a1
+# CHECK-INST: th.vlsseg8w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xfa]
+
+th.vlsseg8w.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg8w.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xfa]
+
+th.vlsseg8w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xf8]
+
+th.vlsseg8bu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg8bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xea]
+
+th.vlsseg8bu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg8bu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xea]
+
+th.vlsseg8bu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8bu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xb5,0xe8]
+
+th.vlsseg8hu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg8hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xea]
+
+th.vlsseg8hu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg8hu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xea]
+
+th.vlsseg8hu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8hu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xb5,0xe8]
+
+th.vlsseg8wu.v v4, (a0), a1
+# CHECK-INST: th.vlsseg8wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xea]
+
+th.vlsseg8wu.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg8wu.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xea]
+
+th.vlsseg8wu.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8wu.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xb5,0xe8]
+
+th.vlsseg8e.v v4, (a0), a1
+# CHECK-INST: th.vlsseg8e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xea]
+
+th.vlsseg8e.v v4, 0(a0), a1
+# CHECK-INST: th.vlsseg8e.v v4, (a0), a1
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xea]
+
+th.vlsseg8e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vlsseg8e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xb5,0xe8]
+
+th.vssseg8b.v v4, (a0), a1
+# CHECK-INST: th.vssseg8b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xea]
+
+th.vssseg8b.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg8b.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xea]
+
+th.vssseg8b.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8b.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xb5,0xe8]
+
+th.vssseg8h.v v4, (a0), a1
+# CHECK-INST: th.vssseg8h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xea]
+
+th.vssseg8h.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg8h.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xea]
+
+th.vssseg8h.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8h.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xb5,0xe8]
+
+th.vssseg8w.v v4, (a0), a1
+# CHECK-INST: th.vssseg8w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xea]
+
+th.vssseg8w.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg8w.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xea]
+
+th.vssseg8w.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8w.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xb5,0xe8]
+
+th.vssseg8e.v v4, (a0), a1
+# CHECK-INST: th.vssseg8e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xea]
+
+th.vssseg8e.v v4, 0(a0), a1
+# CHECK-INST: th.vssseg8e.v v4, (a0), a1
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xea]
+
+th.vssseg8e.v v4, (a0), a1, v0.t
+# CHECK-INST: th.vssseg8e.v v4, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xb5,0xe8]
+
+th.vlxseg2b.v v4, (a0), v12
+# CHECK-INST: th.vlxseg2b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x3e]
+
+th.vlxseg2b.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg2b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x3e]
+
+th.vlxseg2b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg2b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x3c]
+
+th.vlxseg2h.v v4, (a0), v12
+# CHECK-INST: th.vlxseg2h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x3e]
+
+th.vlxseg2h.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg2h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x3e]
+
+th.vlxseg2h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg2h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x3c]
+
+th.vlxseg2w.v v4, (a0), v12
+# CHECK-INST: th.vlxseg2w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x3e]
+
+th.vlxseg2w.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg2w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x3e]
+
+th.vlxseg2w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg2w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x3c]
+
+th.vlxseg2bu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg2bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x2e]
+
+th.vlxseg2bu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg2bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x2e]
+
+th.vlxseg2bu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg2bu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x2c]
+
+th.vlxseg2hu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg2hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x2e]
+
+th.vlxseg2hu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg2hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x2e]
+
+th.vlxseg2hu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg2hu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x2c]
+
+th.vlxseg2wu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg2wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x2e]
+
+th.vlxseg2wu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg2wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x2e]
+
+th.vlxseg2wu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg2wu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x2c]
+
+th.vlxseg2e.v v4, (a0), v12
+# CHECK-INST: th.vlxseg2e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x2e]
+
+th.vlxseg2e.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg2e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x2e]
+
+th.vlxseg2e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg2e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x2c]
+
+th.vsxseg2b.v v4, (a0), v12
+# CHECK-INST: th.vsxseg2b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x2e]
+
+th.vsxseg2b.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg2b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x2e]
+
+th.vsxseg2b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg2b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x2c]
+
+th.vsxseg2h.v v4, (a0), v12
+# CHECK-INST: th.vsxseg2h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x2e]
+
+th.vsxseg2h.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg2h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x2e]
+
+th.vsxseg2h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg2h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x2c]
+
+th.vsxseg2w.v v4, (a0), v12
+# CHECK-INST: th.vsxseg2w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x2e]
+
+th.vsxseg2w.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg2w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x2e]
+
+th.vsxseg2w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg2w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x2c]
+
+th.vsxseg2e.v v4, (a0), v12
+# CHECK-INST: th.vsxseg2e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x2e]
+
+th.vsxseg2e.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg2e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x2e]
+
+th.vsxseg2e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg2e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x2c]
+
+th.vlxseg3b.v v4, (a0), v12
+# CHECK-INST: th.vlxseg3b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x5e]
+
+th.vlxseg3b.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg3b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x5e]
+
+th.vlxseg3b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg3b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x5c]
+
+th.vlxseg3h.v v4, (a0), v12
+# CHECK-INST: th.vlxseg3h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x5e]
+
+th.vlxseg3h.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg3h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x5e]
+
+th.vlxseg3h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg3h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x5c]
+
+th.vlxseg3w.v v4, (a0), v12
+# CHECK-INST: th.vlxseg3w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x5e]
+
+th.vlxseg3w.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg3w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x5e]
+
+th.vlxseg3w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg3w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x5c]
+
+th.vlxseg3bu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg3bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x4e]
+
+th.vlxseg3bu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg3bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x4e]
+
+th.vlxseg3bu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg3bu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x4c]
+
+th.vlxseg3hu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg3hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x4e]
+
+th.vlxseg3hu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg3hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x4e]
+
+th.vlxseg3hu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg3hu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x4c]
+
+th.vlxseg3wu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg3wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x4e]
+
+th.vlxseg3wu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg3wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x4e]
+
+th.vlxseg3wu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg3wu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x4c]
+
+th.vlxseg3e.v v4, (a0), v12
+# CHECK-INST: th.vlxseg3e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x4e]
+
+th.vlxseg3e.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg3e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x4e]
+
+th.vlxseg3e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg3e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x4c]
+
+th.vsxseg3b.v v4, (a0), v12
+# CHECK-INST: th.vsxseg3b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x4e]
+
+th.vsxseg3b.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg3b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x4e]
+
+th.vsxseg3b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg3b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x4c]
+
+th.vsxseg3h.v v4, (a0), v12
+# CHECK-INST: th.vsxseg3h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x4e]
+
+th.vsxseg3h.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg3h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x4e]
+
+th.vsxseg3h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg3h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x4c]
+
+th.vsxseg3w.v v4, (a0), v12
+# CHECK-INST: th.vsxseg3w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x4e]
+
+th.vsxseg3w.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg3w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x4e]
+
+th.vsxseg3w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg3w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x4c]
+
+th.vsxseg3e.v v4, (a0), v12
+# CHECK-INST: th.vsxseg3e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x4e]
+
+th.vsxseg3e.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg3e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x4e]
+
+th.vsxseg3e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg3e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x4c]
+
+th.vlxseg4b.v v4, (a0), v12
+# CHECK-INST: th.vlxseg4b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x7e]
+
+th.vlxseg4b.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg4b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x7e]
+
+th.vlxseg4b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg4b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x7c]
+
+th.vlxseg4h.v v4, (a0), v12
+# CHECK-INST: th.vlxseg4h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x7e]
+
+th.vlxseg4h.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg4h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x7e]
+
+th.vlxseg4h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg4h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x7c]
+
+th.vlxseg4w.v v4, (a0), v12
+# CHECK-INST: th.vlxseg4w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x7e]
+
+th.vlxseg4w.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg4w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x7e]
+
+th.vlxseg4w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg4w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x7c]
+
+th.vlxseg4bu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg4bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x6e]
+
+th.vlxseg4bu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg4bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x6e]
+
+th.vlxseg4bu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg4bu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x6c]
+
+th.vlxseg4hu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg4hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x6e]
+
+th.vlxseg4hu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg4hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x6e]
+
+th.vlxseg4hu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg4hu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x6c]
+
+th.vlxseg4wu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg4wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x6e]
+
+th.vlxseg4wu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg4wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x6e]
+
+th.vlxseg4wu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg4wu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x6c]
+
+th.vlxseg4e.v v4, (a0), v12
+# CHECK-INST: th.vlxseg4e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x6e]
+
+th.vlxseg4e.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg4e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x6e]
+
+th.vlxseg4e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg4e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x6c]
+
+th.vsxseg4b.v v4, (a0), v12
+# CHECK-INST: th.vsxseg4b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x6e]
+
+th.vsxseg4b.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg4b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x6e]
+
+th.vsxseg4b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg4b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x6c]
+
+th.vsxseg4h.v v4, (a0), v12
+# CHECK-INST: th.vsxseg4h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x6e]
+
+th.vsxseg4h.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg4h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x6e]
+
+th.vsxseg4h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg4h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x6c]
+
+th.vsxseg4w.v v4, (a0), v12
+# CHECK-INST: th.vsxseg4w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x6e]
+
+th.vsxseg4w.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg4w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x6e]
+
+th.vsxseg4w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg4w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x6c]
+
+th.vsxseg4e.v v4, (a0), v12
+# CHECK-INST: th.vsxseg4e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x6e]
+
+th.vsxseg4e.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg4e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x6e]
+
+th.vsxseg4e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg4e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x6c]
+
+th.vlxseg5b.v v4, (a0), v12
+# CHECK-INST: th.vlxseg5b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x9e]
+
+th.vlxseg5b.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg5b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x9e]
+
+th.vlxseg5b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg5b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x9c]
+
+th.vlxseg5h.v v4, (a0), v12
+# CHECK-INST: th.vlxseg5h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x9e]
+
+th.vlxseg5h.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg5h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x9e]
+
+th.vlxseg5h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg5h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x9c]
+
+th.vlxseg5w.v v4, (a0), v12
+# CHECK-INST: th.vlxseg5w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x9e]
+
+th.vlxseg5w.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg5w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x9e]
+
+th.vlxseg5w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg5w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x9c]
+
+th.vlxseg5bu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg5bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x8e]
+
+th.vlxseg5bu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg5bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x8e]
+
+th.vlxseg5bu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg5bu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0x8c]
+
+th.vlxseg5hu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg5hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x8e]
+
+th.vlxseg5hu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg5hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x8e]
+
+th.vlxseg5hu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg5hu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0x8c]
+
+th.vlxseg5wu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg5wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x8e]
+
+th.vlxseg5wu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg5wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x8e]
+
+th.vlxseg5wu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg5wu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0x8c]
+
+th.vlxseg5e.v v4, (a0), v12
+# CHECK-INST: th.vlxseg5e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x8e]
+
+th.vlxseg5e.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg5e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x8e]
+
+th.vlxseg5e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg5e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0x8c]
+
+th.vsxseg5b.v v4, (a0), v12
+# CHECK-INST: th.vsxseg5b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x8e]
+
+th.vsxseg5b.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg5b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x8e]
+
+th.vsxseg5b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg5b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0x8c]
+
+th.vsxseg5h.v v4, (a0), v12
+# CHECK-INST: th.vsxseg5h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x8e]
+
+th.vsxseg5h.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg5h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x8e]
+
+th.vsxseg5h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg5h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0x8c]
+
+th.vsxseg5w.v v4, (a0), v12
+# CHECK-INST: th.vsxseg5w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x8e]
+
+th.vsxseg5w.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg5w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x8e]
+
+th.vsxseg5w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg5w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0x8c]
+
+th.vsxseg5e.v v4, (a0), v12
+# CHECK-INST: th.vsxseg5e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x8e]
+
+th.vsxseg5e.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg5e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x8e]
+
+th.vsxseg5e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg5e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0x8c]
+
+th.vlxseg6b.v v4, (a0), v12
+# CHECK-INST: th.vlxseg6b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xbe]
+
+th.vlxseg6b.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg6b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xbe]
+
+th.vlxseg6b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg6b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xbc]
+
+th.vlxseg6h.v v4, (a0), v12
+# CHECK-INST: th.vlxseg6h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xbe]
+
+th.vlxseg6h.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg6h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xbe]
+
+th.vlxseg6h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg6h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xbc]
+
+th.vlxseg6w.v v4, (a0), v12
+# CHECK-INST: th.vlxseg6w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xbe]
+
+th.vlxseg6w.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg6w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xbe]
+
+th.vlxseg6w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg6w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xbc]
+
+th.vlxseg6bu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg6bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xae]
+
+th.vlxseg6bu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg6bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xae]
+
+th.vlxseg6bu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg6bu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xac]
+
+th.vlxseg6hu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg6hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xae]
+
+th.vlxseg6hu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg6hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xae]
+
+th.vlxseg6hu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg6hu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xac]
+
+th.vlxseg6wu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg6wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xae]
+
+th.vlxseg6wu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg6wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xae]
+
+th.vlxseg6wu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg6wu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xac]
+
+th.vlxseg6e.v v4, (a0), v12
+# CHECK-INST: th.vlxseg6e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xae]
+
+th.vlxseg6e.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg6e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xae]
+
+th.vlxseg6e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg6e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xac]
+
+th.vsxseg6b.v v4, (a0), v12
+# CHECK-INST: th.vsxseg6b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xae]
+
+th.vsxseg6b.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg6b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xae]
+
+th.vsxseg6b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg6b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xac]
+
+th.vsxseg6h.v v4, (a0), v12
+# CHECK-INST: th.vsxseg6h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xae]
+
+th.vsxseg6h.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg6h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xae]
+
+th.vsxseg6h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg6h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xac]
+
+th.vsxseg6w.v v4, (a0), v12
+# CHECK-INST: th.vsxseg6w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xae]
+
+th.vsxseg6w.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg6w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xae]
+
+th.vsxseg6w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg6w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xac]
+
+th.vsxseg6e.v v4, (a0), v12
+# CHECK-INST: th.vsxseg6e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xae]
+
+th.vsxseg6e.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg6e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xae]
+
+th.vsxseg6e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg6e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xac]
+
+th.vlxseg7b.v v4, (a0), v12
+# CHECK-INST: th.vlxseg7b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xde]
+
+th.vlxseg7b.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg7b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xde]
+
+th.vlxseg7b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg7b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xdc]
+
+th.vlxseg7h.v v4, (a0), v12
+# CHECK-INST: th.vlxseg7h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xde]
+
+th.vlxseg7h.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg7h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xde]
+
+th.vlxseg7h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg7h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xdc]
+
+th.vlxseg7w.v v4, (a0), v12
+# CHECK-INST: th.vlxseg7w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xde]
+
+th.vlxseg7w.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg7w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xde]
+
+th.vlxseg7w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg7w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xdc]
+
+th.vlxseg7bu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg7bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xce]
+
+th.vlxseg7bu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg7bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xce]
+
+th.vlxseg7bu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg7bu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xcc]
+
+th.vlxseg7hu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg7hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xce]
+
+th.vlxseg7hu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg7hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xce]
+
+th.vlxseg7hu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg7hu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xcc]
+
+th.vlxseg7wu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg7wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xce]
+
+th.vlxseg7wu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg7wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xce]
+
+th.vlxseg7wu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg7wu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xcc]
+
+th.vlxseg7e.v v4, (a0), v12
+# CHECK-INST: th.vlxseg7e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xce]
+
+th.vlxseg7e.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg7e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xce]
+
+th.vlxseg7e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg7e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xcc]
+
+th.vsxseg7b.v v4, (a0), v12
+# CHECK-INST: th.vsxseg7b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xce]
+
+th.vsxseg7b.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg7b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xce]
+
+th.vsxseg7b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg7b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xcc]
+
+th.vsxseg7h.v v4, (a0), v12
+# CHECK-INST: th.vsxseg7h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xce]
+
+th.vsxseg7h.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg7h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xce]
+
+th.vsxseg7h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg7h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xcc]
+
+th.vsxseg7w.v v4, (a0), v12
+# CHECK-INST: th.vsxseg7w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xce]
+
+th.vsxseg7w.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg7w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xce]
+
+th.vsxseg7w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg7w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xcc]
+
+th.vsxseg7e.v v4, (a0), v12
+# CHECK-INST: th.vsxseg7e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xce]
+
+th.vsxseg7e.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg7e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xce]
+
+th.vsxseg7e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg7e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xcc]
+
+th.vlxseg8b.v v4, (a0), v12
+# CHECK-INST: th.vlxseg8b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xfe]
+
+th.vlxseg8b.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg8b.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xfe]
+
+th.vlxseg8b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg8b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xfc]
+
+th.vlxseg8h.v v4, (a0), v12
+# CHECK-INST: th.vlxseg8h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xfe]
+
+th.vlxseg8h.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg8h.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xfe]
+
+th.vlxseg8h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg8h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xfc]
+
+th.vlxseg8w.v v4, (a0), v12
+# CHECK-INST: th.vlxseg8w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xfe]
+
+th.vlxseg8w.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg8w.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xfe]
+
+th.vlxseg8w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg8w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xfc]
+
+th.vlxseg8bu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg8bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xee]
+
+th.vlxseg8bu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg8bu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xee]
+
+th.vlxseg8bu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg8bu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x02,0xc5,0xec]
+
+th.vlxseg8hu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg8hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xee]
+
+th.vlxseg8hu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg8hu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xee]
+
+th.vlxseg8hu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg8hu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x52,0xc5,0xec]
+
+th.vlxseg8wu.v v4, (a0), v12
+# CHECK-INST: th.vlxseg8wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xee]
+
+th.vlxseg8wu.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg8wu.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xee]
+
+th.vlxseg8wu.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg8wu.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x62,0xc5,0xec]
+
+th.vlxseg8e.v v4, (a0), v12
+# CHECK-INST: th.vlxseg8e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xee]
+
+th.vlxseg8e.v v4, 0(a0), v12
+# CHECK-INST: th.vlxseg8e.v v4, (a0), v12
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xee]
+
+th.vlxseg8e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vlxseg8e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x07,0x72,0xc5,0xec]
+
+th.vsxseg8b.v v4, (a0), v12
+# CHECK-INST: th.vsxseg8b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xee]
+
+th.vsxseg8b.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg8b.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xee]
+
+th.vsxseg8b.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg8b.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x02,0xc5,0xec]
+
+th.vsxseg8h.v v4, (a0), v12
+# CHECK-INST: th.vsxseg8h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xee]
+
+th.vsxseg8h.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg8h.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xee]
+
+th.vsxseg8h.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg8h.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x52,0xc5,0xec]
+
+th.vsxseg8w.v v4, (a0), v12
+# CHECK-INST: th.vsxseg8w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xee]
+
+th.vsxseg8w.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg8w.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xee]
+
+th.vsxseg8w.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg8w.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x62,0xc5,0xec]
+
+th.vsxseg8e.v v4, (a0), v12
+# CHECK-INST: th.vsxseg8e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xee]
+
+th.vsxseg8e.v v4, 0(a0), v12
+# CHECK-INST: th.vsxseg8e.v v4, (a0), v12
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xee]
+
+th.vsxseg8e.v v4, (a0), v12, v0.t
+# CHECK-INST: th.vsxseg8e.v v4, (a0), v12, v0.t
+# CHECK-ENCODING: [0x27,0x72,0xc5,0xec]
+
+th.vlseg2bff.v v4, (a0)
+# CHECK-INST: th.vlseg2bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x33]
+
+th.vlseg2bff.v v4, 0(a0)
+# CHECK-INST: th.vlseg2bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x33]
+
+th.vlseg2bff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2bff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x31]
+
+th.vlseg2hff.v v4, (a0)
+# CHECK-INST: th.vlseg2hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x33]
+
+th.vlseg2hff.v v4, 0(a0)
+# CHECK-INST: th.vlseg2hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x33]
+
+th.vlseg2hff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2hff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x31]
+
+th.vlseg2wff.v v4, (a0)
+# CHECK-INST: th.vlseg2wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x33]
+
+th.vlseg2wff.v v4, 0(a0)
+# CHECK-INST: th.vlseg2wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x33]
+
+th.vlseg2wff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2wff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x31]
+
+th.vlseg2buff.v v4, (a0)
+# CHECK-INST: th.vlseg2buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x23]
+
+th.vlseg2buff.v v4, 0(a0)
+# CHECK-INST: th.vlseg2buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x23]
+
+th.vlseg2buff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2buff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x21]
+
+th.vlseg2huff.v v4, (a0)
+# CHECK-INST: th.vlseg2huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x23]
+
+th.vlseg2huff.v v4, 0(a0)
+# CHECK-INST: th.vlseg2huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x23]
+
+th.vlseg2huff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2huff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x21]
+
+th.vlseg2wuff.v v4, (a0)
+# CHECK-INST: th.vlseg2wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x23]
+
+th.vlseg2wuff.v v4, 0(a0)
+# CHECK-INST: th.vlseg2wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x23]
+
+th.vlseg2wuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2wuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x21]
+
+th.vlseg2eff.v v4, (a0)
+# CHECK-INST: th.vlseg2eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x23]
+
+th.vlseg2eff.v v4, 0(a0)
+# CHECK-INST: th.vlseg2eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x23]
+
+th.vlseg2eff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg2eff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x21]
+
+th.vlseg3bff.v v4, (a0)
+# CHECK-INST: th.vlseg3bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x53]
+
+th.vlseg3bff.v v4, 0(a0)
+# CHECK-INST: th.vlseg3bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x53]
+
+th.vlseg3bff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3bff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x51]
+
+th.vlseg3hff.v v4, (a0)
+# CHECK-INST: th.vlseg3hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x53]
+
+th.vlseg3hff.v v4, 0(a0)
+# CHECK-INST: th.vlseg3hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x53]
+
+th.vlseg3hff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3hff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x51]
+
+th.vlseg3wff.v v4, (a0)
+# CHECK-INST: th.vlseg3wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x53]
+
+th.vlseg3wff.v v4, 0(a0)
+# CHECK-INST: th.vlseg3wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x53]
+
+th.vlseg3wff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3wff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x51]
+
+th.vlseg3buff.v v4, (a0)
+# CHECK-INST: th.vlseg3buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x43]
+
+th.vlseg3buff.v v4, 0(a0)
+# CHECK-INST: th.vlseg3buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x43]
+
+th.vlseg3buff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3buff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x41]
+
+th.vlseg3huff.v v4, (a0)
+# CHECK-INST: th.vlseg3huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x43]
+
+th.vlseg3huff.v v4, 0(a0)
+# CHECK-INST: th.vlseg3huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x43]
+
+th.vlseg3huff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3huff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x41]
+
+th.vlseg3wuff.v v4, (a0)
+# CHECK-INST: th.vlseg3wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x43]
+
+th.vlseg3wuff.v v4, 0(a0)
+# CHECK-INST: th.vlseg3wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x43]
+
+th.vlseg3wuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3wuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x41]
+
+th.vlseg3eff.v v4, (a0)
+# CHECK-INST: th.vlseg3eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x43]
+
+th.vlseg3eff.v v4, 0(a0)
+# CHECK-INST: th.vlseg3eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x43]
+
+th.vlseg3eff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg3eff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x41]
+
+th.vlseg4bff.v v4, (a0)
+# CHECK-INST: th.vlseg4bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x73]
+
+th.vlseg4bff.v v4, 0(a0)
+# CHECK-INST: th.vlseg4bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x73]
+
+th.vlseg4bff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4bff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x71]
+
+th.vlseg4hff.v v4, (a0)
+# CHECK-INST: th.vlseg4hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x73]
+
+th.vlseg4hff.v v4, 0(a0)
+# CHECK-INST: th.vlseg4hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x73]
+
+th.vlseg4hff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4hff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x71]
+
+th.vlseg4wff.v v4, (a0)
+# CHECK-INST: th.vlseg4wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x73]
+
+th.vlseg4wff.v v4, 0(a0)
+# CHECK-INST: th.vlseg4wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x73]
+
+th.vlseg4wff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4wff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x71]
+
+th.vlseg4buff.v v4, (a0)
+# CHECK-INST: th.vlseg4buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x63]
+
+th.vlseg4buff.v v4, 0(a0)
+# CHECK-INST: th.vlseg4buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x63]
+
+th.vlseg4buff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4buff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x61]
+
+th.vlseg4huff.v v4, (a0)
+# CHECK-INST: th.vlseg4huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x63]
+
+th.vlseg4huff.v v4, 0(a0)
+# CHECK-INST: th.vlseg4huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x63]
+
+th.vlseg4huff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4huff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x61]
+
+th.vlseg4wuff.v v4, (a0)
+# CHECK-INST: th.vlseg4wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x63]
+
+th.vlseg4wuff.v v4, 0(a0)
+# CHECK-INST: th.vlseg4wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x63]
+
+th.vlseg4wuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4wuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x61]
+
+th.vlseg4eff.v v4, (a0)
+# CHECK-INST: th.vlseg4eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x63]
+
+th.vlseg4eff.v v4, 0(a0)
+# CHECK-INST: th.vlseg4eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x63]
+
+th.vlseg4eff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg4eff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x61]
+
+th.vlseg5bff.v v4, (a0)
+# CHECK-INST: th.vlseg5bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x93]
+
+th.vlseg5bff.v v4, 0(a0)
+# CHECK-INST: th.vlseg5bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x93]
+
+th.vlseg5bff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5bff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x91]
+
+th.vlseg5hff.v v4, (a0)
+# CHECK-INST: th.vlseg5hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x93]
+
+th.vlseg5hff.v v4, 0(a0)
+# CHECK-INST: th.vlseg5hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x93]
+
+th.vlseg5hff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5hff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x91]
+
+th.vlseg5wff.v v4, (a0)
+# CHECK-INST: th.vlseg5wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x93]
+
+th.vlseg5wff.v v4, 0(a0)
+# CHECK-INST: th.vlseg5wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x93]
+
+th.vlseg5wff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5wff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x91]
+
+th.vlseg5buff.v v4, (a0)
+# CHECK-INST: th.vlseg5buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x83]
+
+th.vlseg5buff.v v4, 0(a0)
+# CHECK-INST: th.vlseg5buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0x83]
+
+th.vlseg5buff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5buff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0x81]
+
+th.vlseg5huff.v v4, (a0)
+# CHECK-INST: th.vlseg5huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x83]
+
+th.vlseg5huff.v v4, 0(a0)
+# CHECK-INST: th.vlseg5huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0x83]
+
+th.vlseg5huff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5huff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0x81]
+
+th.vlseg5wuff.v v4, (a0)
+# CHECK-INST: th.vlseg5wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x83]
+
+th.vlseg5wuff.v v4, 0(a0)
+# CHECK-INST: th.vlseg5wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0x83]
+
+th.vlseg5wuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5wuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0x81]
+
+th.vlseg5eff.v v4, (a0)
+# CHECK-INST: th.vlseg5eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x83]
+
+th.vlseg5eff.v v4, 0(a0)
+# CHECK-INST: th.vlseg5eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0x83]
+
+th.vlseg5eff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg5eff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0x81]
+
+th.vlseg6bff.v v4, (a0)
+# CHECK-INST: th.vlseg6bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xb3]
+
+th.vlseg6bff.v v4, 0(a0)
+# CHECK-INST: th.vlseg6bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xb3]
+
+th.vlseg6bff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6bff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xb1]
+
+th.vlseg6hff.v v4, (a0)
+# CHECK-INST: th.vlseg6hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xb3]
+
+th.vlseg6hff.v v4, 0(a0)
+# CHECK-INST: th.vlseg6hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xb3]
+
+th.vlseg6hff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6hff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xb1]
+
+th.vlseg6wff.v v4, (a0)
+# CHECK-INST: th.vlseg6wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xb3]
+
+th.vlseg6wff.v v4, 0(a0)
+# CHECK-INST: th.vlseg6wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xb3]
+
+th.vlseg6wff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6wff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xb1]
+
+th.vlseg6buff.v v4, (a0)
+# CHECK-INST: th.vlseg6buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xa3]
+
+th.vlseg6buff.v v4, 0(a0)
+# CHECK-INST: th.vlseg6buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xa3]
+
+th.vlseg6buff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6buff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xa1]
+
+th.vlseg6huff.v v4, (a0)
+# CHECK-INST: th.vlseg6huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xa3]
+
+th.vlseg6huff.v v4, 0(a0)
+# CHECK-INST: th.vlseg6huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xa3]
+
+th.vlseg6huff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6huff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xa1]
+
+th.vlseg6wuff.v v4, (a0)
+# CHECK-INST: th.vlseg6wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xa3]
+
+th.vlseg6wuff.v v4, 0(a0)
+# CHECK-INST: th.vlseg6wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xa3]
+
+th.vlseg6wuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6wuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xa1]
+
+th.vlseg6eff.v v4, (a0)
+# CHECK-INST: th.vlseg6eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xa3]
+
+th.vlseg6eff.v v4, 0(a0)
+# CHECK-INST: th.vlseg6eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xa3]
+
+th.vlseg6eff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg6eff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0xa1]
+
+th.vlseg7bff.v v4, (a0)
+# CHECK-INST: th.vlseg7bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xd3]
+
+th.vlseg7bff.v v4, 0(a0)
+# CHECK-INST: th.vlseg7bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xd3]
+
+th.vlseg7bff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7bff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xd1]
+
+th.vlseg7hff.v v4, (a0)
+# CHECK-INST: th.vlseg7hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xd3]
+
+th.vlseg7hff.v v4, 0(a0)
+# CHECK-INST: th.vlseg7hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xd3]
+
+th.vlseg7hff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7hff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xd1]
+
+th.vlseg7wff.v v4, (a0)
+# CHECK-INST: th.vlseg7wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xd3]
+
+th.vlseg7wff.v v4, 0(a0)
+# CHECK-INST: th.vlseg7wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xd3]
+
+th.vlseg7wff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7wff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xd1]
+
+th.vlseg7buff.v v4, (a0)
+# CHECK-INST: th.vlseg7buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xc3]
+
+th.vlseg7buff.v v4, 0(a0)
+# CHECK-INST: th.vlseg7buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xc3]
+
+th.vlseg7buff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7buff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xc1]
+
+th.vlseg7huff.v v4, (a0)
+# CHECK-INST: th.vlseg7huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xc3]
+
+th.vlseg7huff.v v4, 0(a0)
+# CHECK-INST: th.vlseg7huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xc3]
+
+th.vlseg7huff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7huff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xc1]
+
+th.vlseg7wuff.v v4, (a0)
+# CHECK-INST: th.vlseg7wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xc3]
+
+th.vlseg7wuff.v v4, 0(a0)
+# CHECK-INST: th.vlseg7wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xc3]
+
+th.vlseg7wuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7wuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xc1]
+
+th.vlseg7eff.v v4, (a0)
+# CHECK-INST: th.vlseg7eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xc3]
+
+th.vlseg7eff.v v4, 0(a0)
+# CHECK-INST: th.vlseg7eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xc3]
+
+th.vlseg7eff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg7eff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0xc1]
+
+th.vlseg8bff.v v4, (a0)
+# CHECK-INST: th.vlseg8bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xf3]
+
+th.vlseg8bff.v v4, 0(a0)
+# CHECK-INST: th.vlseg8bff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xf3]
+
+th.vlseg8bff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8bff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xf1]
+
+th.vlseg8hff.v v4, (a0)
+# CHECK-INST: th.vlseg8hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xf3]
+
+th.vlseg8hff.v v4, 0(a0)
+# CHECK-INST: th.vlseg8hff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xf3]
+
+th.vlseg8hff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8hff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xf1]
+
+th.vlseg8wff.v v4, (a0)
+# CHECK-INST: th.vlseg8wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xf3]
+
+th.vlseg8wff.v v4, 0(a0)
+# CHECK-INST: th.vlseg8wff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xf3]
+
+th.vlseg8wff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8wff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xf1]
+
+th.vlseg8buff.v v4, (a0)
+# CHECK-INST: th.vlseg8buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xe3]
+
+th.vlseg8buff.v v4, 0(a0)
+# CHECK-INST: th.vlseg8buff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x02,0x05,0xe3]
+
+th.vlseg8buff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8buff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x02,0x05,0xe1]
+
+th.vlseg8huff.v v4, (a0)
+# CHECK-INST: th.vlseg8huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xe3]
+
+th.vlseg8huff.v v4, 0(a0)
+# CHECK-INST: th.vlseg8huff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x52,0x05,0xe3]
+
+th.vlseg8huff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8huff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x52,0x05,0xe1]
+
+th.vlseg8wuff.v v4, (a0)
+# CHECK-INST: th.vlseg8wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xe3]
+
+th.vlseg8wuff.v v4, 0(a0)
+# CHECK-INST: th.vlseg8wuff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x62,0x05,0xe3]
+
+th.vlseg8wuff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8wuff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x62,0x05,0xe1]
+
+th.vlseg8eff.v v4, (a0)
+# CHECK-INST: th.vlseg8eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xe3]
+
+th.vlseg8eff.v v4, 0(a0)
+# CHECK-INST: th.vlseg8eff.v v4, (a0)
+# CHECK-ENCODING: [0x07,0x72,0x05,0xe3]
+
+th.vlseg8eff.v v4, (a0), v0.t
+# CHECK-INST: th.vlseg8eff.v v4, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x72,0x05,0xe1]
+
+th.vamoaddw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoaddw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x06]
+
+th.vamoaddw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoaddw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x02]
+
+th.vamoaddd.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoaddd.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x06]
+
+th.vamoaddd.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoaddd.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x02]
+
+th.vamoaddw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoaddw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x04]
+
+th.vamoaddw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoaddw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x00]
+
+th.vamoaddd.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoaddd.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x04]
+
+th.vamoaddd.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoaddd.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x00]
+
+th.vamoswapw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoswapw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x0e]
+
+th.vamoswapw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoswapw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x0a]
+
+th.vamoswapd.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoswapd.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x0e]
+
+th.vamoswapd.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoswapd.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x0a]
+
+th.vamoswapw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoswapw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x0c]
+
+th.vamoswapw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoswapw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x08]
+
+th.vamoswapd.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoswapd.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x0c]
+
+th.vamoswapd.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoswapd.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x08]
+
+th.vamoxorw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoxorw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x26]
+
+th.vamoxorw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoxorw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x22]
+
+th.vamoxord.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoxord.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x26]
+
+th.vamoxord.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoxord.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x22]
+
+th.vamoxorw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoxorw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x24]
+
+th.vamoxorw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoxorw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x20]
+
+th.vamoxord.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoxord.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x24]
+
+th.vamoxord.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoxord.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x20]
+
+th.vamoandw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoandw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x66]
+
+th.vamoandw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoandw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x62]
+
+th.vamoandd.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoandd.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x66]
+
+th.vamoandd.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoandd.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x62]
+
+th.vamoandw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoandw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x64]
+
+th.vamoandw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoandw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x60]
+
+th.vamoandd.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoandd.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x64]
+
+th.vamoandd.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoandd.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x60]
+
+th.vamoorw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoorw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x46]
+
+th.vamoorw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoorw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x42]
+
+th.vamoord.v v4, v8, (a1), v4
+# CHECK-INST: th.vamoord.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x46]
+
+th.vamoord.v zero, v8, (a1), v4
+# CHECK-INST: th.vamoord.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x42]
+
+th.vamoorw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoorw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x44]
+
+th.vamoorw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoorw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x40]
+
+th.vamoord.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoord.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x44]
+
+th.vamoord.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamoord.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x40]
+
+th.vamominw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamominw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x86]
+
+th.vamominw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamominw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x82]
+
+th.vamomind.v v4, v8, (a1), v4
+# CHECK-INST: th.vamomind.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x86]
+
+th.vamomind.v zero, v8, (a1), v4
+# CHECK-INST: th.vamomind.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x82]
+
+th.vamominw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamominw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x84]
+
+th.vamominw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamominw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0x80]
+
+th.vamomind.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomind.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x84]
+
+th.vamomind.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomind.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0x80]
+
+th.vamomaxw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamomaxw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xa6]
+
+th.vamomaxw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamomaxw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xa2]
+
+th.vamomaxd.v v4, v8, (a1), v4
+# CHECK-INST: th.vamomaxd.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xa6]
+
+th.vamomaxd.v zero, v8, (a1), v4
+# CHECK-INST: th.vamomaxd.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xa2]
+
+th.vamomaxw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xa4]
+
+th.vamomaxw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xa0]
+
+th.vamomaxd.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxd.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xa4]
+
+th.vamomaxd.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxd.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xa0]
+
+th.vamominuw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamominuw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xc6]
+
+th.vamominuw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamominuw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xc2]
+
+th.vamominud.v v4, v8, (a1), v4
+# CHECK-INST: th.vamominud.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xc6]
+
+th.vamominud.v zero, v8, (a1), v4
+# CHECK-INST: th.vamominud.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xc2]
+
+th.vamominuw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamominuw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xc4]
+
+th.vamominuw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamominuw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xc0]
+
+th.vamominud.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamominud.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xc4]
+
+th.vamominud.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamominud.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xc0]
+
+th.vamomaxuw.v v4, v8, (a1), v4
+# CHECK-INST: th.vamomaxuw.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xe6]
+
+th.vamomaxuw.v zero, v8, (a1), v4
+# CHECK-INST: th.vamomaxuw.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xe2]
+
+th.vamomaxud.v v4, v8, (a1), v4
+# CHECK-INST: th.vamomaxud.v v4, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xe6]
+
+th.vamomaxud.v zero, v8, (a1), v4
+# CHECK-INST: th.vamomaxud.v x0, v8, (a1), v4
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xe2]
+
+th.vamomaxuw.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxuw.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xe4]
+
+th.vamomaxuw.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxuw.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xe2,0x85,0xe0]
+
+th.vamomaxud.v v4, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxud.v v4, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xe4]
+
+th.vamomaxud.v zero, v8, (a1), v4, v0.t
+# CHECK-INST: th.vamomaxud.v x0, v8, (a1), v4, v0.t
+# CHECK-ENCODING: [0x2f,0xf2,0x85,0xe0]
+
+th.vadd.vv v4, v8, v12
+# CHECK-INST: th.vadd.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x02]
+
+th.vadd.vx v4, v8, a1
+# CHECK-INST: th.vadd.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x02]
+
+th.vadd.vi v4, v8, 15
+# CHECK-INST: th.vadd.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x02]
+
+th.vadd.vi v4, v8, -16
+# CHECK-INST: th.vadd.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x02]
+
+th.vadd.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vadd.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x00]
+
+th.vadd.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vadd.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x00]
+
+th.vadd.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vadd.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x00]
+
+th.vadd.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vadd.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x00]
+
+th.vsub.vv v4, v8, v12
+# CHECK-INST: th.vsub.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x0a]
+
+th.vsub.vx v4, v8, a1
+# CHECK-INST: th.vsub.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x0a]
+
+th.vrsub.vx v4, v8, a1
+# CHECK-INST: th.vrsub.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x0e]
+
+th.vrsub.vi v4, v8, 15
+# CHECK-INST: th.vrsub.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x0e]
+
+th.vrsub.vi v4, v8, -16
+# CHECK-INST: th.vrsub.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x0e]
+
+th.vsub.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vsub.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x08]
+
+th.vsub.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vsub.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x08]
+
+th.vrsub.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vrsub.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x0c]
+
+th.vrsub.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vrsub.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x0c]
+
+th.vrsub.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vrsub.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x0c]
+
+th.vwcvt.x.x.v v4, v8
+# CHECK-INST: th.vwcvt.x.x.v v4, v8
+# CHECK-ENCODING: [0x57,0x62,0x80,0xc6]
+
+th.vwcvtu.x.x.v v4, v8
+# CHECK-INST: th.vwcvtu.x.x.v v4, v8
+# CHECK-ENCODING: [0x57,0x62,0x80,0xc2]
+
+th.vwcvt.x.x.v v4, v8, v0.t
+# CHECK-INST: th.vwcvt.x.x.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x62,0x80,0xc4]
+
+th.vwcvtu.x.x.v v4, v8, v0.t
+# CHECK-INST: th.vwcvtu.x.x.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x62,0x80,0xc0]
+
+th.vwaddu.vv v4, v8, v12
+# CHECK-INST: th.vwaddu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xc2]
+
+th.vwaddu.vx v4, v8, a1
+# CHECK-INST: th.vwaddu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xc2]
+
+th.vwaddu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vwaddu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xc0]
+
+th.vwaddu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vwaddu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xc0]
+
+th.vwsubu.vv v4, v8, v12
+# CHECK-INST: th.vwsubu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xca]
+
+th.vwsubu.vx v4, v8, a1
+# CHECK-INST: th.vwsubu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xca]
+
+th.vwsubu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vwsubu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xc8]
+
+th.vwsubu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vwsubu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xc8]
+
+th.vwadd.vv v4, v8, v12
+# CHECK-INST: th.vwadd.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xc6]
+
+th.vwadd.vx v4, v8, a1
+# CHECK-INST: th.vwadd.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xc6]
+
+th.vwadd.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vwadd.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xc4]
+
+th.vwadd.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vwadd.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xc4]
+
+th.vwsub.vv v4, v8, v12
+# CHECK-INST: th.vwsub.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xce]
+
+th.vwsub.vx v4, v8, a1
+# CHECK-INST: th.vwsub.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xce]
+
+th.vwsub.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vwsub.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xcc]
+
+th.vwsub.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vwsub.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xcc]
+
+th.vwaddu.wv v4, v8, v12
+# CHECK-INST: th.vwaddu.wv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xd2]
+
+th.vwaddu.wx v4, v8, a1
+# CHECK-INST: th.vwaddu.wx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xd2]
+
+th.vwaddu.wv v4, v8, v12, v0.t
+# CHECK-INST: th.vwaddu.wv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xd0]
+
+th.vwaddu.wx v4, v8, a1, v0.t
+# CHECK-INST: th.vwaddu.wx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xd0]
+
+th.vwsubu.wv v4, v8, v12
+# CHECK-INST: th.vwsubu.wv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xda]
+
+th.vwsubu.wx v4, v8, a1
+# CHECK-INST: th.vwsubu.wx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xda]
+
+th.vwsubu.wv v4, v8, v12, v0.t
+# CHECK-INST: th.vwsubu.wv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xd8]
+
+th.vwsubu.wx v4, v8, a1, v0.t
+# CHECK-INST: th.vwsubu.wx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xd8]
+
+th.vwadd.wv v4, v8, v12
+# CHECK-INST: th.vwadd.wv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xd6]
+
+th.vwadd.wx v4, v8, a1
+# CHECK-INST: th.vwadd.wx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xd6]
+
+th.vwadd.wv v4, v8, v12, v0.t
+# CHECK-INST: th.vwadd.wv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xd4]
+
+th.vwadd.wx v4, v8, a1, v0.t
+# CHECK-INST: th.vwadd.wx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xd4]
+
+th.vwsub.wv v4, v8, v12
+# CHECK-INST: th.vwsub.wv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xde]
+
+th.vwsub.wx v4, v8, a1
+# CHECK-INST: th.vwsub.wx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xde]
+
+th.vwsub.wv v4, v8, v12, v0.t
+# CHECK-INST: th.vwsub.wv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xdc]
+
+th.vwsub.wx v4, v8, a1, v0.t
+# CHECK-INST: th.vwsub.wx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xdc]
+
+th.vadc.vvm v4, v8, v12, v0
+# CHECK-INST: th.vadc.vvm v4, v8, v12, v0
+# CHECK-ENCODING: [0x57,0x02,0x86,0x42]
+
+th.vadc.vxm v4, v8, a1, v0
+# CHECK-INST: th.vadc.vxm v4, v8, a1, v0
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x42]
+
+th.vadc.vim v4, v8, 15, v0
+# CHECK-INST: th.vadc.vim v4, v8, 15, v0
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x42]
+
+th.vadc.vim v4, v8, -16, v0
+# CHECK-INST: th.vadc.vim v4, v8, -16, v0
+# CHECK-ENCODING: [0x57,0x32,0x88,0x42]
+
+th.vmadc.vvm v4, v8, v12, v0
+# CHECK-INST: th.vmadc.vvm v4, v8, v12, v0
+# CHECK-ENCODING: [0x57,0x02,0x86,0x46]
+
+th.vmadc.vxm v4, v8, a1, v0
+# CHECK-INST: th.vmadc.vxm v4, v8, a1, v0
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x46]
+
+th.vmadc.vim v4, v8, 15, v0
+# CHECK-INST: th.vmadc.vim v4, v8, 15, v0
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x46]
+
+th.vmadc.vim v4, v8, -16, v0
+# CHECK-INST: th.vmadc.vim v4, v8, -16, v0
+# CHECK-ENCODING: [0x57,0x32,0x88,0x46]
+
+th.vsbc.vvm v4, v8, v12, v0
+# CHECK-INST: th.vsbc.vvm v4, v8, v12, v0
+# CHECK-ENCODING: [0x57,0x02,0x86,0x4a]
+
+th.vsbc.vxm v4, v8, a1, v0
+# CHECK-INST: th.vsbc.vxm v4, v8, a1, v0
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x4a]
+
+th.vmsbc.vvm v4, v8, v12, v0
+# CHECK-INST: th.vmsbc.vvm v4, v8, v12, v0
+# CHECK-ENCODING: [0x57,0x02,0x86,0x4e]
+
+th.vmsbc.vxm v4, v8, a1, v0
+# CHECK-INST: th.vmsbc.vxm v4, v8, a1, v0
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x4e]
+
+th.vnot.v v4, v8
+# CHECK-INST: th.vnot.v v4, v8
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x2e]
+
+th.vnot.v v4, v8, v0.t
+# CHECK-INST: th.vnot.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x2c]
+
+th.vand.vv v4, v8, v12
+# CHECK-INST: th.vand.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x26]
+
+th.vand.vx v4, v8, a1
+# CHECK-INST: th.vand.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x26]
+
+th.vand.vi v4, v8, 15
+# CHECK-INST: th.vand.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x26]
+
+th.vand.vi v4, v8, -16
+# CHECK-INST: th.vand.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x26]
+
+th.vand.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vand.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x24]
+
+th.vand.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vand.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x24]
+
+th.vand.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vand.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x24]
+
+th.vand.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vand.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x24]
+
+th.vor.vv v4, v8, v12
+# CHECK-INST: th.vor.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x2a]
+
+th.vor.vx v4, v8, a1
+# CHECK-INST: th.vor.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x2a]
+
+th.vor.vi v4, v8, 15
+# CHECK-INST: th.vor.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x2a]
+
+th.vor.vi v4, v8, -16
+# CHECK-INST: th.vor.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x2a]
+
+th.vor.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vor.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x28]
+
+th.vor.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vor.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x28]
+
+th.vor.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vor.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x28]
+
+th.vor.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vor.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x28]
+
+th.vxor.vv v4, v8, v12
+# CHECK-INST: th.vxor.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x2e]
+
+th.vxor.vx v4, v8, a1
+# CHECK-INST: th.vxor.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x2e]
+
+th.vxor.vi v4, v8, 15
+# CHECK-INST: th.vxor.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x2e]
+
+th.vxor.vi v4, v8, -16
+# CHECK-INST: th.vxor.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x2e]
+
+th.vxor.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vxor.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x2c]
+
+th.vxor.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vxor.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x2c]
+
+th.vxor.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vxor.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x2c]
+
+th.vxor.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vxor.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x2c]
+
+th.vsll.vv v4, v8, v12
+# CHECK-INST: th.vsll.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x96]
+
+th.vsll.vx v4, v8, a1
+# CHECK-INST: th.vsll.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x96]
+
+th.vsll.vi v4, v8, 1
+# CHECK-INST: th.vsll.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0x96]
+
+th.vsll.vi v4, v8, 31
+# CHECK-INST: th.vsll.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x96]
+
+th.vsll.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vsll.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x94]
+
+th.vsll.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vsll.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x94]
+
+th.vsll.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vsll.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0x94]
+
+th.vsll.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vsll.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x94]
+
+th.vsrl.vv v4, v8, v12
+# CHECK-INST: th.vsrl.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xa2]
+
+th.vsrl.vx v4, v8, a1
+# CHECK-INST: th.vsrl.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xa2]
+
+th.vsrl.vi v4, v8, 1
+# CHECK-INST: th.vsrl.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xa2]
+
+th.vsrl.vi v4, v8, 31
+# CHECK-INST: th.vsrl.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xa2]
+
+th.vsrl.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vsrl.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xa0]
+
+th.vsrl.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vsrl.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xa0]
+
+th.vsrl.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vsrl.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xa0]
+
+th.vsrl.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vsrl.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xa0]
+
+th.vsra.vv v4, v8, v12
+# CHECK-INST: th.vsra.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xa6]
+
+th.vsra.vx v4, v8, a1
+# CHECK-INST: th.vsra.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xa6]
+
+th.vsra.vi v4, v8, 1
+# CHECK-INST: th.vsra.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xa6]
+
+th.vsra.vi v4, v8, 31
+# CHECK-INST: th.vsra.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xa6]
+
+th.vsra.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vsra.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xa4]
+
+th.vsra.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vsra.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xa4]
+
+th.vsra.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vsra.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xa4]
+
+th.vsra.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vsra.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xa4]
+
+th.vnsrl.vv v4, v8, v12
+# CHECK-INST: th.vnsrl.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xb2]
+
+th.vnsrl.vx v4, v8, a1
+# CHECK-INST: th.vnsrl.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xb2]
+
+th.vnsrl.vi v4, v8, 1
+# CHECK-INST: th.vnsrl.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xb2]
+
+th.vnsrl.vi v4, v8, 31
+# CHECK-INST: th.vnsrl.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xb2]
+
+th.vnsrl.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vnsrl.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xb0]
+
+th.vnsrl.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vnsrl.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xb0]
+
+th.vnsrl.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vnsrl.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xb0]
+
+th.vnsrl.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vnsrl.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xb0]
+
+th.vnsra.vv v4, v8, v12
+# CHECK-INST: th.vnsra.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xb6]
+
+th.vnsra.vx v4, v8, a1
+# CHECK-INST: th.vnsra.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xb6]
+
+th.vnsra.vi v4, v8, 1
+# CHECK-INST: th.vnsra.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xb6]
+
+th.vnsra.vi v4, v8, 31
+# CHECK-INST: th.vnsra.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xb6]
+
+th.vnsra.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vnsra.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xb4]
+
+th.vnsra.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vnsra.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xb4]
+
+th.vnsra.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vnsra.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xb4]
+
+th.vnsra.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vnsra.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xb4]
+
+th.vmsgt.vv v4, v8, v12
+# CHECK-INST: th.vmslt.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x6e]
+
+th.vmsgtu.vv v4, v8, v12
+# CHECK-INST: th.vmsltu.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x6a]
+
+th.vmsge.vv v4, v8, v12
+# CHECK-INST: th.vmsle.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x76]
+
+th.vmsgeu.vv v4, v8, v12
+# CHECK-INST: th.vmsleu.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x72]
+
+th.vmsgt.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmslt.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x6c]
+
+th.vmsgtu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmsltu.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x68]
+
+th.vmsge.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmsle.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x74]
+
+th.vmsgeu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmsleu.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x02,0xc4,0x70]
+
+th.vmsge.vx v4, v8, a1
+# CHECK-INST: th.vmslt.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x6e]
+# CHECK-INST: th.vmnot.m v4, v4
+# CHECK-ENCODING: [0x57,0x22,0x42,0x76]
+
+th.vmsgeu.vx v4, v8, a1
+# CHECK-INST: th.vmsltu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x6a]
+# CHECK-INST: th.vmnot.m v4, v4
+# CHECK-ENCODING: [0x57,0x22,0x42,0x76]
+
+th.vmsge.vx v8, v12, a2, v0.t
+# CHECK-INST: th.vmslt.vx v8, v12, a2, v0.t
+# CHECK-ENCODING: [0x57,0x44,0xc6,0x6c]
+# CHECK-INST: th.vmxor.mm v8, v8, v0
+# CHECK-ENCODING: [0x57,0x24,0x80,0x6e]
+
+th.vmsgeu.vx v8, v12, a2, v0.t
+# CHECK-INST: th.vmsltu.vx v8, v12, a2, v0.t
+# CHECK-ENCODING: [0x57,0x44,0xc6,0x68]
+# CHECK-INST: th.vmxor.mm v8, v8, v0
+# CHECK-ENCODING: [0x57,0x24,0x80,0x6e]
+
+th.vmsge.vx v4, v8, a1, v0.t, v12
+# CHECK-INST: th.vmslt.vx v12, v8, a1
+# TODO: GCC produces vmslt.vx v12, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc6,0x85,0x6e]
+# CHECK-INST: th.vmandnot.mm v4, v4, v12
+# CHECK-ENCODING: [0x57,0x22,0x46,0x62]
+
+th.vmsgeu.vx v4, v8, a1, v0.t, v12
+# CHECK-INST: th.vmsltu.vx v12, v8, a1
+# TODO: GCC produces vmsltu.vx v12, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc6,0x85,0x6a]
+# CHECK-INST: th.vmandnot.mm v4, v4, v12
+# CHECK-ENCODING: [0x57,0x22,0x46,0x62]
+
+th.vmslt.vi v4, v8, 16
+# CHECK-INST: th.vmsle.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x76]
+
+th.vmslt.vi v4, v8, -15
+# CHECK-INST: th.vmsle.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x76]
+
+th.vmsltu.vi v4, v8, 16
+# CHECK-INST: th.vmsleu.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x72]
+
+th.vmsltu.vi v4, v8, -15
+# CHECK-INST: th.vmsleu.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x72]
+
+th.vmsge.vi v4, v8, 16
+# CHECK-INST: th.vmsgt.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x7e]
+
+th.vmsge.vi v4, v8, -15
+# CHECK-INST: th.vmsgt.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x7e]
+
+th.vmsgeu.vi v4, v8, 16
+# CHECK-INST: th.vmsgtu.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x7a]
+
+th.vmsgeu.vi v4, v8, -15
+# CHECK-INST: th.vmsgtu.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x7a]
+
+th.vmslt.vi v4, v8, 16, v0.t
+# CHECK-INST: th.vmsle.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x74]
+
+th.vmslt.vi v4, v8, -15, v0.t
+# CHECK-INST: th.vmsle.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x74]
+
+th.vmsltu.vi v4, v8, 16, v0.t
+# CHECK-INST: th.vmsleu.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x70]
+
+th.vmsltu.vi v4, v8, -15, v0.t
+# CHECK-INST: th.vmsleu.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x70]
+
+th.vmsge.vi v4, v8, 16, v0.t
+# CHECK-INST: th.vmsgt.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x7c]
+
+th.vmsge.vi v4, v8, -15, v0.t
+# CHECK-INST: th.vmsgt.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x7c]
+
+th.vmsgeu.vi v4, v8, 16, v0.t
+# CHECK-INST: th.vmsgtu.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x78]
+
+th.vmsgeu.vi v4, v8, -15, v0.t
+# CHECK-INST: th.vmsgtu.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x78]
+
+th.vmseq.vv v4, v8, v12
+# CHECK-INST: th.vmseq.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x62]
+
+th.vmseq.vx v4, v8, a1
+# CHECK-INST: th.vmseq.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x62]
+
+th.vmseq.vi v4, v8, 15
+# CHECK-INST: th.vmseq.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x62]
+
+th.vmseq.vi v4, v8, -16
+# CHECK-INST: th.vmseq.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x62]
+
+th.vmseq.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmseq.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x60]
+
+th.vmseq.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmseq.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x60]
+
+th.vmseq.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vmseq.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x60]
+
+th.vmseq.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vmseq.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x60]
+
+th.vmsne.vv v4, v8, v12
+# CHECK-INST: th.vmsne.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x66]
+
+th.vmsne.vx v4, v8, a1
+# CHECK-INST: th.vmsne.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x66]
+
+th.vmsne.vi v4, v8, 15
+# CHECK-INST: th.vmsne.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x66]
+
+th.vmsne.vi v4, v8, -16
+# CHECK-INST: th.vmsne.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x66]
+
+th.vmsne.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmsne.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x64]
+
+th.vmsne.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmsne.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x64]
+
+th.vmsne.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vmsne.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x64]
+
+th.vmsne.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vmsne.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x64]
+
+th.vmsltu.vv v4, v8, v12
+# CHECK-INST: th.vmsltu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x6a]
+
+th.vmsltu.vx v4, v8, a1
+# CHECK-INST: th.vmsltu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x6a]
+
+th.vmsltu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmsltu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x68]
+
+th.vmsltu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmsltu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x68]
+
+th.vmslt.vv v4, v8, v12
+# CHECK-INST: th.vmslt.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x6e]
+
+th.vmslt.vx v4, v8, a1
+# CHECK-INST: th.vmslt.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x6e]
+
+th.vmslt.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmslt.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x6c]
+
+th.vmslt.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmslt.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x6c]
+
+th.vmsleu.vv v4, v8, v12
+# CHECK-INST: th.vmsleu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x72]
+
+th.vmsleu.vx v4, v8, a1
+# CHECK-INST: th.vmsleu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x72]
+
+th.vmsleu.vi v4, v8, 15
+# CHECK-INST: th.vmsleu.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x72]
+
+th.vmsleu.vi v4, v8, -16
+# CHECK-INST: th.vmsleu.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x72]
+
+th.vmsleu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmsleu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x70]
+
+th.vmsleu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmsleu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x70]
+
+th.vmsleu.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vmsleu.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x70]
+
+th.vmsleu.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vmsleu.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x70]
+
+th.vmsle.vv v4, v8, v12
+# CHECK-INST: th.vmsle.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x76]
+
+th.vmsle.vx v4, v8, a1
+# CHECK-INST: th.vmsle.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x76]
+
+th.vmsle.vi v4, v8, 15
+# CHECK-INST: th.vmsle.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x76]
+
+th.vmsle.vi v4, v8, -16
+# CHECK-INST: th.vmsle.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x76]
+
+th.vmsle.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmsle.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x74]
+
+th.vmsle.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmsle.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x74]
+
+th.vmsle.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vmsle.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x74]
+
+th.vmsle.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vmsle.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x74]
+
+th.vmsgtu.vx v4, v8, a1
+# CHECK-INST: th.vmsgtu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x7a]
+
+th.vmsgtu.vi v4, v8, 15
+# CHECK-INST: th.vmsgtu.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x7a]
+
+th.vmsgtu.vi v4, v8, -16
+# CHECK-INST: th.vmsgtu.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x7a]
+
+th.vmsgtu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmsgtu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x78]
+
+th.vmsgtu.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vmsgtu.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x78]
+
+th.vmsgtu.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vmsgtu.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x78]
+
+th.vmsgt.vx v4, v8, a1
+# CHECK-INST: th.vmsgt.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x7e]
+
+th.vmsgt.vi v4, v8, 15
+# CHECK-INST: th.vmsgt.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x7e]
+
+th.vmsgt.vi v4, v8, -16
+# CHECK-INST: th.vmsgt.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x7e]
+
+th.vmsgt.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmsgt.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x7c]
+
+th.vmsgt.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vmsgt.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x7c]
+
+th.vmsgt.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vmsgt.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x7c]
+
+th.vminu.vv v4, v8, v12
+# CHECK-INST: th.vminu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x12]
+
+th.vminu.vx v4, v8, a1
+# CHECK-INST: th.vminu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x12]
+
+th.vminu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vminu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x10]
+
+th.vminu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vminu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x10]
+
+th.vmin.vv v4, v8, v12
+# CHECK-INST: th.vmin.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x16]
+
+th.vmin.vx v4, v8, a1
+# CHECK-INST: th.vmin.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x16]
+
+th.vmin.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmin.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x14]
+
+th.vmin.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmin.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x14]
+
+th.vmaxu.vv v4, v8, v12
+# CHECK-INST: th.vmaxu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x1a]
+
+th.vmaxu.vx v4, v8, a1
+# CHECK-INST: th.vmaxu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x1a]
+
+th.vmaxu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmaxu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x18]
+
+th.vmaxu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmaxu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x18]
+
+th.vmax.vv v4, v8, v12
+# CHECK-INST: th.vmax.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x1e]
+
+th.vmax.vx v4, v8, a1
+# CHECK-INST: th.vmax.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x1e]
+
+th.vmax.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmax.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x1c]
+
+th.vmax.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmax.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x1c]
+
+th.vmul.vv v4, v8, v12
+# CHECK-INST: th.vmul.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x96]
+
+th.vmul.vx v4, v8, a1
+# CHECK-INST: th.vmul.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x96]
+
+th.vmul.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmul.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x94]
+
+th.vmul.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmul.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x94]
+
+th.vmulh.vv v4, v8, v12
+# CHECK-INST: th.vmulh.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x9e]
+
+th.vmulh.vx v4, v8, a1
+# CHECK-INST: th.vmulh.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x9e]
+
+th.vmulh.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmulh.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x9c]
+
+th.vmulh.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmulh.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x9c]
+
+th.vmulhu.vv v4, v8, v12
+# CHECK-INST: th.vmulhu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x92]
+
+th.vmulhu.vx v4, v8, a1
+# CHECK-INST: th.vmulhu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x92]
+
+th.vmulhu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmulhu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x90]
+
+th.vmulhu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmulhu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x90]
+
+th.vmulhsu.vv v4, v8, v12
+# CHECK-INST: th.vmulhsu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x9a]
+
+th.vmulhsu.vx v4, v8, a1
+# CHECK-INST: th.vmulhsu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x9a]
+
+th.vmulhsu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmulhsu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x98]
+
+th.vmulhsu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vmulhsu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x98]
+
+th.vwmul.vv v4, v8, v12
+# CHECK-INST: th.vwmul.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xee]
+
+th.vwmul.vx v4, v8, a1
+# CHECK-INST: th.vwmul.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xee]
+
+th.vwmul.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vwmul.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xec]
+
+th.vwmul.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vwmul.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xec]
+
+th.vwmulu.vv v4, v8, v12
+# CHECK-INST: th.vwmulu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xe2]
+
+th.vwmulu.vx v4, v8, a1
+# CHECK-INST: th.vwmulu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xe2]
+
+th.vwmulu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vwmulu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xe0]
+
+th.vwmulu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vwmulu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xe0]
+
+th.vwmulsu.vv v4, v8, v12
+# CHECK-INST: th.vwmulsu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0xea]
+
+th.vwmulsu.vx v4, v8, a1
+# CHECK-INST: th.vwmulsu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xea]
+
+th.vwmulsu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vwmulsu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xe8]
+
+th.vwmulsu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vwmulsu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xe8]
+
+th.vmacc.vv v4, v12, v8
+# CHECK-INST: th.vmacc.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x22,0x86,0xb6]
+
+th.vmacc.vx v4, a1, v8
+# CHECK-INST: th.vmacc.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xb6]
+
+th.vmacc.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vmacc.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xb4]
+
+th.vmacc.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vmacc.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xb4]
+
+th.vnmsac.vv v4, v12, v8
+# CHECK-INST: th.vnmsac.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x22,0x86,0xbe]
+
+th.vnmsac.vx v4, a1, v8
+# CHECK-INST: th.vnmsac.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xbe]
+
+th.vnmsac.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vnmsac.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xbc]
+
+th.vnmsac.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vnmsac.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xbc]
+
+th.vmadd.vv v4, v12, v8
+# CHECK-INST: th.vmadd.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x22,0x86,0xa6]
+
+th.vmadd.vx v4, a1, v8
+# CHECK-INST: th.vmadd.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xa6]
+
+th.vmadd.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vmadd.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xa4]
+
+th.vmadd.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vmadd.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xa4]
+
+th.vnmsub.vv v4, v12, v8
+# CHECK-INST: th.vnmsub.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x22,0x86,0xae]
+
+th.vnmsub.vx v4, a1, v8
+# CHECK-INST: th.vnmsub.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xae]
+
+th.vnmsub.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vnmsub.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xac]
+
+th.vnmsub.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vnmsub.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xac]
+
+th.vwmaccu.vv v4, v12, v8
+# CHECK-INST: th.vwmaccu.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x22,0x86,0xf2]
+
+th.vwmaccu.vx v4, a1, v8
+# CHECK-INST: th.vwmaccu.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xf2]
+
+th.vwmaccu.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vwmaccu.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xf0]
+
+th.vwmaccu.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwmaccu.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xf0]
+
+th.vwmacc.vv v4, v12, v8
+# CHECK-INST: th.vwmacc.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x22,0x86,0xf6]
+
+th.vwmacc.vx v4, a1, v8
+# CHECK-INST: th.vwmacc.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xf6]
+
+th.vwmacc.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vwmacc.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xf4]
+
+th.vwmacc.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwmacc.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xf4]
+
+th.vwmaccsu.vv v4, v12, v8
+# CHECK-INST: th.vwmaccsu.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x22,0x86,0xfa]
+
+th.vwmaccsu.vx v4, a1, v8
+# CHECK-INST: th.vwmaccsu.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xfa]
+
+th.vwmaccsu.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vwmaccsu.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0xf8]
+
+th.vwmaccsu.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwmaccsu.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xf8]
+
+th.vwmaccus.vx v4, a1, v8
+# CHECK-INST: th.vwmaccus.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xfe]
+
+th.vwmaccus.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwmaccus.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0xfc]
+
+th.vdivu.vv v4, v8, v12
+# CHECK-INST: th.vdivu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x82]
+
+th.vdivu.vx v4, v8, a1
+# CHECK-INST: th.vdivu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x82]
+
+th.vdivu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vdivu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x80]
+
+th.vdivu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vdivu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x80]
+
+th.vdiv.vv v4, v8, v12
+# CHECK-INST: th.vdiv.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x86]
+
+th.vdiv.vx v4, v8, a1
+# CHECK-INST: th.vdiv.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x86]
+
+th.vdiv.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vdiv.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x84]
+
+th.vdiv.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vdiv.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x84]
+
+th.vremu.vv v4, v8, v12
+# CHECK-INST: th.vremu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x8a]
+
+th.vremu.vx v4, v8, a1
+# CHECK-INST: th.vremu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x8a]
+
+th.vremu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vremu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x88]
+
+th.vremu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vremu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x88]
+
+th.vrem.vv v4, v8, v12
+# CHECK-INST: th.vrem.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x8e]
+
+th.vrem.vx v4, v8, a1
+# CHECK-INST: th.vrem.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x8e]
+
+th.vrem.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vrem.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x8c]
+
+th.vrem.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vrem.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x8c]
+
+th.vmerge.vvm v4, v8, v12, v0
+# CHECK-INST: th.vmerge.vvm v4, v8, v12, v0
+# CHECK-ENCODING: [0x57,0x02,0x86,0x5c]
+
+th.vmerge.vxm v4, v8, a1, v0
+# CHECK-INST: th.vmerge.vxm v4, v8, a1, v0
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x5c]
+
+th.vmerge.vim v4, v8, 15, v0
+# CHECK-INST: th.vmerge.vim v4, v8, 15, v0
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x5c]
+
+th.vmerge.vim v4, v8, -16, v0
+# CHECK-INST: th.vmerge.vim v4, v8, -16, v0
+# CHECK-ENCODING: [0x57,0x32,0x88,0x5c]
+
+th.vmv.v.v v8, v12
+# CHECK-INST: th.vmv.v.v v8, v12
+# CHECK-ENCODING: [0x57,0x04,0x06,0x5e]
+
+th.vmv.v.x v8, a1
+# CHECK-INST: th.vmv.v.x v8, a1
+# CHECK-ENCODING: [0x57,0xc4,0x05,0x5e]
+
+th.vmv.v.i v8, 15
+# CHECK-INST: th.vmv.v.i v8, 15
+# CHECK-ENCODING: [0x57,0xb4,0x07,0x5e]
+
+th.vmv.v.i v8, -16
+# CHECK-INST: th.vmv.v.i v8, -16
+# CHECK-ENCODING: [0x57,0x34,0x08,0x5e]
+
+th.vsaddu.vv v4, v8, v12
+# CHECK-INST: th.vsaddu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x82]
+
+th.vsaddu.vx v4, v8, a1
+# CHECK-INST: th.vsaddu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x82]
+
+th.vsaddu.vi v4, v8, 15
+# CHECK-INST: th.vsaddu.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x82]
+
+th.vsaddu.vi v4, v8, -16
+# CHECK-INST: th.vsaddu.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x82]
+
+th.vsaddu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vsaddu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x80]
+
+th.vsaddu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vsaddu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x80]
+
+th.vsaddu.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vsaddu.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x80]
+
+th.vsaddu.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vsaddu.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x80]
+
+th.vsadd.vv v4, v8, v12
+# CHECK-INST: th.vsadd.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x86]
+
+th.vsadd.vx v4, v8, a1
+# CHECK-INST: th.vsadd.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x86]
+
+th.vsadd.vi v4, v8, 15
+# CHECK-INST: th.vsadd.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x86]
+
+th.vsadd.vi v4, v8, -16
+# CHECK-INST: th.vsadd.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x86]
+
+th.vsadd.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vsadd.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x84]
+
+th.vsadd.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vsadd.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x84]
+
+th.vsadd.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vsadd.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x84]
+
+th.vsadd.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vsadd.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x84]
+
+th.vssubu.vv v4, v8, v12
+# CHECK-INST: th.vssubu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x8a]
+
+th.vssubu.vx v4, v8, a1
+# CHECK-INST: th.vssubu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x8a]
+
+th.vssubu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vssubu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x88]
+
+th.vssubu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vssubu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x88]
+
+th.vssub.vv v4, v8, v12
+# CHECK-INST: th.vssub.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x8e]
+
+th.vssub.vx v4, v8, a1
+# CHECK-INST: th.vssub.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x8e]
+
+th.vssub.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vssub.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x8c]
+
+th.vssub.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vssub.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x8c]
+
+th.vaadd.vv v4, v8, v12
+# CHECK-INST: th.vaadd.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x92]
+
+th.vaadd.vx v4, v8, a1
+# CHECK-INST: th.vaadd.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x92]
+
+th.vaadd.vi v4, v8, 15
+# CHECK-INST: th.vaadd.vi v4, v8, 15
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x92]
+
+th.vaadd.vi v4, v8, -16
+# CHECK-INST: th.vaadd.vi v4, v8, -16
+# CHECK-ENCODING: [0x57,0x32,0x88,0x92]
+
+th.vaadd.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vaadd.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x90]
+
+th.vaadd.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vaadd.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x90]
+
+th.vaadd.vi v4, v8, 15, v0.t
+# CHECK-INST: th.vaadd.vi v4, v8, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x87,0x90]
+
+th.vaadd.vi v4, v8, -16, v0.t
+# CHECK-INST: th.vaadd.vi v4, v8, -16, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x88,0x90]
+
+th.vasub.vv v4, v8, v12
+# CHECK-INST: th.vasub.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x9a]
+
+th.vasub.vx v4, v8, a1
+# CHECK-INST: th.vasub.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x9a]
+
+th.vasub.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vasub.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x98]
+
+th.vasub.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vasub.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x98]
+
+th.vsmul.vv v4, v8, v12
+# CHECK-INST: th.vsmul.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x9e]
+
+th.vsmul.vx v4, v8, a1
+# CHECK-INST: th.vsmul.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x9e]
+
+th.vsmul.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vsmul.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x9c]
+
+th.vsmul.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vsmul.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x9c]
+
+th.vwsmaccu.vv v4, v12, v8
+# CHECK-INST: th.vwsmaccu.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x02,0x86,0xf2]
+
+th.vwsmaccu.vx v4, a1, v8
+# CHECK-INST: th.vwsmaccu.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xf2]
+
+th.vwsmacc.vv v4, v12, v8
+# CHECK-INST: th.vwsmacc.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x02,0x86,0xf6]
+
+th.vwsmacc.vx v4, a1, v8
+# CHECK-INST: th.vwsmacc.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xf6]
+
+th.vwsmaccsu.vv v4, v12, v8
+# CHECK-INST: th.vwsmaccsu.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x02,0x86,0xfa]
+
+th.vwsmaccsu.vx v4, a1, v8
+# CHECK-INST: th.vwsmaccsu.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xfa]
+
+th.vwsmaccus.vx v4, a1, v8
+# CHECK-INST: th.vwsmaccus.vx v4, a1, v8
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xfe]
+
+th.vwsmaccu.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vwsmaccu.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xf0]
+
+th.vwsmaccu.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwsmaccu.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xf0]
+
+th.vwsmacc.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vwsmacc.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xf4]
+
+th.vwsmacc.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwsmacc.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xf4]
+
+th.vwsmaccsu.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vwsmaccsu.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xf8]
+
+th.vwsmaccsu.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwsmaccsu.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xf8]
+
+th.vwsmaccus.vx v4, a1, v8, v0.t
+# CHECK-INST: th.vwsmaccus.vx v4, a1, v8, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xfc]
+
+th.vssrl.vv v4, v8, v12
+# CHECK-INST: th.vssrl.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xaa]
+
+th.vssrl.vx v4, v8, a1
+# CHECK-INST: th.vssrl.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xaa]
+
+th.vssrl.vi v4, v8, 1
+# CHECK-INST: th.vssrl.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xaa]
+
+th.vssrl.vi v4, v8, 31
+# CHECK-INST: th.vssrl.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xaa]
+
+th.vssrl.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vssrl.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xa8]
+
+th.vssrl.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vssrl.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xa8]
+
+th.vssrl.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vssrl.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xa8]
+
+th.vssrl.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vssrl.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xa8]
+
+th.vssra.vv v4, v8, v12
+# CHECK-INST: th.vssra.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xae]
+
+th.vssra.vx v4, v8, a1
+# CHECK-INST: th.vssra.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xae]
+
+th.vssra.vi v4, v8, 1
+# CHECK-INST: th.vssra.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xae]
+
+th.vssra.vi v4, v8, 31
+# CHECK-INST: th.vssra.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xae]
+
+th.vssra.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vssra.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xac]
+
+th.vssra.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vssra.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xac]
+
+th.vssra.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vssra.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xac]
+
+th.vssra.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vssra.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xac]
+
+th.vnclipu.vv v4, v8, v12
+# CHECK-INST: th.vnclipu.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xba]
+
+th.vnclipu.vx v4, v8, a1
+# CHECK-INST: th.vnclipu.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xba]
+
+th.vnclipu.vi v4, v8, 1
+# CHECK-INST: th.vnclipu.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xba]
+
+th.vnclipu.vi v4, v8, 31
+# CHECK-INST: th.vnclipu.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xba]
+
+th.vnclipu.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vnclipu.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xb8]
+
+th.vnclipu.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vnclipu.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xb8]
+
+th.vnclipu.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vnclipu.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xb8]
+
+th.vnclipu.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vnclipu.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xb8]
+
+th.vnclip.vv v4, v8, v12
+# CHECK-INST: th.vnclip.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xbe]
+
+th.vnclip.vx v4, v8, a1
+# CHECK-INST: th.vnclip.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xbe]
+
+th.vnclip.vi v4, v8, 1
+# CHECK-INST: th.vnclip.vi v4, v8, 1
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xbe]
+
+th.vnclip.vi v4, v8, 31
+# CHECK-INST: th.vnclip.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xbe]
+
+th.vnclip.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vnclip.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xbc]
+
+th.vnclip.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vnclip.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0xbc]
+
+th.vnclip.vi v4, v8, 1, v0.t
+# CHECK-INST: th.vnclip.vi v4, v8, 1, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x80,0xbc]
+
+th.vnclip.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vnclip.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0xbc]
+
+th.vfadd.vv v4, v8, v12
+# CHECK-INST: th.vfadd.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x02]
+
+th.vfadd.vf v4, v8, fa2
+# CHECK-INST: th.vfadd.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x02]
+
+th.vfadd.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfadd.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x00]
+
+th.vfadd.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfadd.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x00]
+
+th.vfsub.vv v4, v8, v12
+# CHECK-INST: th.vfsub.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x0a]
+
+th.vfsub.vf v4, v8, fa2
+# CHECK-INST: th.vfsub.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x0a]
+
+th.vfsub.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfsub.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x08]
+
+th.vfsub.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfsub.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x08]
+
+th.vfrsub.vf v4, v8, fa2
+# CHECK-INST: th.vfrsub.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x9e]
+
+th.vfrsub.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfrsub.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x9c]
+
+th.vfwadd.vv v4, v8, v12
+# CHECK-INST: th.vfwadd.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0xc2]
+
+th.vfwadd.vf v4, v8, fa2
+# CHECK-INST: th.vfwadd.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0xc2]
+
+th.vfwadd.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfwadd.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xc0]
+
+th.vfwadd.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfwadd.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xc0]
+
+th.vfwsub.vv v4, v8, v12
+# CHECK-INST: th.vfwsub.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0xca]
+
+th.vfwsub.vf v4, v8, fa2
+# CHECK-INST: th.vfwsub.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0xca]
+
+th.vfwsub.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfwsub.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xc8]
+
+th.vfwsub.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfwsub.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xc8]
+
+th.vfwadd.wv v4, v8, v12
+# CHECK-INST: th.vfwadd.wv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0xd2]
+
+th.vfwadd.wf v4, v8, fa2
+# CHECK-INST: th.vfwadd.wf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0xd2]
+
+th.vfwadd.wv v4, v8, v12, v0.t
+# CHECK-INST: th.vfwadd.wv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xd0]
+
+th.vfwadd.wf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfwadd.wf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xd0]
+
+th.vfwsub.wv v4, v8, v12
+# CHECK-INST: th.vfwsub.wv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0xda]
+
+th.vfwsub.wf v4, v8, fa2
+# CHECK-INST: th.vfwsub.wf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0xda]
+
+th.vfwsub.wv v4, v8, v12, v0.t
+# CHECK-INST: th.vfwsub.wv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xd8]
+
+th.vfwsub.wf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfwsub.wf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xd8]
+
+th.vfmul.vv v4, v8, v12
+# CHECK-INST: th.vfmul.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x92]
+
+th.vfmul.vf v4, v8, fa2
+# CHECK-INST: th.vfmul.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x92]
+
+th.vfmul.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfmul.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x90]
+
+th.vfmul.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfmul.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x90]
+
+th.vfdiv.vv v4, v8, v12
+# CHECK-INST: th.vfdiv.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x82]
+
+th.vfdiv.vf v4, v8, fa2
+# CHECK-INST: th.vfdiv.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x82]
+
+th.vfdiv.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfdiv.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x80]
+
+th.vfdiv.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfdiv.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x80]
+
+th.vfrdiv.vf v4, v8, fa2
+# CHECK-INST: th.vfrdiv.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x86]
+
+th.vfrdiv.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfrdiv.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x84]
+
+th.vfwmul.vv v4, v8, v12
+# CHECK-INST: th.vfwmul.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0xe2]
+
+th.vfwmul.vf v4, v8, fa2
+# CHECK-INST: th.vfwmul.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0xe2]
+
+th.vfwmul.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfwmul.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xe0]
+
+th.vfwmul.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfwmul.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xe0]
+
+th.vfmadd.vv v4, v12, v8
+# CHECK-INST: th.vfmadd.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xa2]
+
+th.vfmadd.vf v4, fa2, v8
+# CHECK-INST: th.vfmadd.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xa2]
+
+th.vfnmadd.vv v4, v12, v8
+# CHECK-INST: th.vfnmadd.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xa6]
+
+th.vfnmadd.vf v4, fa2, v8
+# CHECK-INST: th.vfnmadd.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xa6]
+
+th.vfmsub.vv v4, v12, v8
+# CHECK-INST: th.vfmsub.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xaa]
+
+th.vfmsub.vf v4, fa2, v8
+# CHECK-INST: th.vfmsub.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xaa]
+
+th.vfnmsub.vv v4, v12, v8
+# CHECK-INST: th.vfnmsub.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xae]
+
+th.vfnmsub.vf v4, fa2, v8
+# CHECK-INST: th.vfnmsub.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xae]
+
+th.vfmadd.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfmadd.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xa0]
+
+th.vfmadd.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfmadd.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xa0]
+
+th.vfnmadd.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfnmadd.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xa4]
+
+th.vfnmadd.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfnmadd.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xa4]
+
+th.vfmsub.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfmsub.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xa8]
+
+th.vfmsub.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfmsub.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xa8]
+
+th.vfnmsub.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfnmsub.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xac]
+
+th.vfnmsub.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfnmsub.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xac]
+
+th.vfmacc.vv v4, v12, v8
+# CHECK-INST: th.vfmacc.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xb2]
+
+th.vfmacc.vf v4, fa2, v8
+# CHECK-INST: th.vfmacc.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xb2]
+
+th.vfnmacc.vv v4, v12, v8
+# CHECK-INST: th.vfnmacc.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xb6]
+
+th.vfnmacc.vf v4, fa2, v8
+# CHECK-INST: th.vfnmacc.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xb6]
+
+th.vfmsac.vv v4, v12, v8
+# CHECK-INST: th.vfmsac.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xba]
+
+th.vfmsac.vf v4, fa2, v8
+# CHECK-INST: th.vfmsac.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xba]
+
+th.vfnmsac.vv v4, v12, v8
+# CHECK-INST: th.vfnmsac.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xbe]
+
+th.vfnmsac.vf v4, fa2, v8
+# CHECK-INST: th.vfnmsac.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xbe]
+
+th.vfmacc.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfmacc.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xb0]
+
+th.vfmacc.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfmacc.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xb0]
+
+th.vfnmacc.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfnmacc.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xb4]
+
+th.vfnmacc.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfnmacc.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xb4]
+
+th.vfmsac.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfmsac.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xb8]
+
+th.vfmsac.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfmsac.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xb8]
+
+th.vfnmsac.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfnmsac.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xbc]
+
+th.vfnmsac.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfnmsac.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xbc]
+
+th.vfwmacc.vv v4, v12, v8
+# CHECK-INST: th.vfwmacc.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xf2]
+
+th.vfwmacc.vf v4, fa2, v8
+# CHECK-INST: th.vfwmacc.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xf2]
+
+th.vfwnmacc.vv v4, v12, v8
+# CHECK-INST: th.vfwnmacc.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xf6]
+
+th.vfwnmacc.vf v4, fa2, v8
+# CHECK-INST: th.vfwnmacc.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xf6]
+
+th.vfwmsac.vv v4, v12, v8
+# CHECK-INST: th.vfwmsac.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xfa]
+
+th.vfwmsac.vf v4, fa2, v8
+# CHECK-INST: th.vfwmsac.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xfa]
+
+th.vfwnmsac.vv v4, v12, v8
+# CHECK-INST: th.vfwnmsac.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0xfe]
+
+th.vfwnmsac.vf v4, fa2, v8
+# CHECK-INST: th.vfwnmsac.vf v4, fa2, v8
+# CHECK-ENCODING: [0x57,0x52,0x86,0xfe]
+
+th.vfwmacc.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfwmacc.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xf0]
+
+th.vfwmacc.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfwmacc.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xf0]
+
+th.vfwnmacc.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfwnmacc.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xf4]
+
+th.vfwnmacc.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfwnmacc.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xf4]
+
+th.vfwmsac.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfwmsac.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xf8]
+
+th.vfwmsac.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfwmsac.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xf8]
+
+th.vfwnmsac.vv v4, v12, v8, v0.t
+# CHECK-INST: th.vfwnmsac.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xfc]
+
+th.vfwnmsac.vf v4, fa2, v8, v0.t
+# CHECK-INST: th.vfwnmsac.vf v4, fa2, v8, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0xfc]
+
+th.vfsqrt.v v4, v8
+# CHECK-INST: th.vfsqrt.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x80,0x8e]
+
+th.vfsqrt.v v4, v8, v0.t
+# CHECK-INST: th.vfsqrt.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x80,0x8c]
+
+th.vfmin.vv v4, v8, v12
+# CHECK-INST: th.vfmin.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x12]
+
+th.vfmin.vf v4, v8, fa2
+# CHECK-INST: th.vfmin.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x12]
+
+th.vfmax.vv v4, v8, v12
+# CHECK-INST: th.vfmax.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x1a]
+
+th.vfmax.vf v4, v8, fa2
+# CHECK-INST: th.vfmax.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x1a]
+
+th.vfmin.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfmin.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x10]
+
+th.vfmin.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfmin.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x10]
+
+th.vfmax.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfmax.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x18]
+
+th.vfmax.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfmax.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x18]
+
+th.vfsgnj.vv v4, v8, v12
+# CHECK-INST: th.vfsgnj.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x22]
+
+th.vfsgnj.vf v4, v8, fa2
+# CHECK-INST: th.vfsgnj.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x22]
+
+th.vfsgnjn.vv v4, v8, v12
+# CHECK-INST: th.vfsgnjn.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x26]
+
+th.vfsgnjn.vf v4, v8, fa2
+# CHECK-INST: th.vfsgnjn.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x26]
+
+th.vfsgnjx.vv v4, v8, v12
+# CHECK-INST: th.vfsgnjx.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x2a]
+
+th.vfsgnjx.vf v4, v8, fa2
+# CHECK-INST: th.vfsgnjx.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x2a]
+
+th.vfsgnj.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfsgnj.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x20]
+
+th.vfsgnj.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfsgnj.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x20]
+
+th.vfsgnjn.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfsgnjn.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x24]
+
+th.vfsgnjn.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfsgnjn.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x24]
+
+th.vfsgnjx.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vfsgnjx.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x28]
+
+th.vfsgnjx.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vfsgnjx.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x28]
+
+th.vmfgt.vv v4, v8, v12
+# CHECK-INST: th.vmflt.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0xc4,0x6e]
+
+th.vmfge.vv v4, v8, v12
+# CHECK-INST: th.vmfle.vv v4, v12, v8
+# CHECK-ENCODING: [0x57,0x12,0xc4,0x66]
+
+th.vmfgt.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmflt.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0xc4,0x6c]
+
+th.vmfge.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmfle.vv v4, v12, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0xc4,0x64]
+
+th.vmfeq.vv v4, v8, v12
+# CHECK-INST: th.vmfeq.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x62]
+
+th.vmfeq.vf v4, v8, fa2
+# CHECK-INST: th.vmfeq.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x62]
+
+th.vmfne.vv v4, v8, v12
+# CHECK-INST: th.vmfne.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x72]
+
+th.vmfne.vf v4, v8, fa2
+# CHECK-INST: th.vmfne.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x72]
+
+th.vmflt.vv v4, v8, v12
+# CHECK-INST: th.vmflt.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x6e]
+
+th.vmflt.vf v4, v8, fa2
+# CHECK-INST: th.vmflt.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x6e]
+
+th.vmfle.vv v4, v8, v12
+# CHECK-INST: th.vmfle.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x66]
+
+th.vmfle.vf v4, v8, fa2
+# CHECK-INST: th.vmfle.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x66]
+
+th.vmfgt.vf v4, v8, fa2
+# CHECK-INST: th.vmfgt.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x76]
+
+th.vmfge.vf v4, v8, fa2
+# CHECK-INST: th.vmfge.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x7e]
+
+th.vmfeq.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmfeq.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x60]
+
+th.vmfeq.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vmfeq.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x60]
+
+th.vmfne.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmfne.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x70]
+
+th.vmfne.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vmfne.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x70]
+
+th.vmflt.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmflt.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x6c]
+
+th.vmflt.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vmflt.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x6c]
+
+th.vmfle.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmfle.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x64]
+
+th.vmfle.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vmfle.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x64]
+
+th.vmfgt.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vmfgt.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x74]
+
+th.vmfge.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vmfge.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x7c]
+
+th.vmford.vv v4, v8, v12
+# CHECK-INST: th.vmford.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x6a]
+
+th.vmford.vf v4, v8, fa2
+# CHECK-INST: th.vmford.vf v4, v8, fa2
+# CHECK-ENCODING: [0x57,0x52,0x86,0x6a]
+
+th.vmford.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vmford.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x68]
+
+th.vmford.vf v4, v8, fa2, v0.t
+# CHECK-INST: th.vmford.vf v4, v8, fa2, v0.t
+# CHECK-ENCODING: [0x57,0x52,0x86,0x68]
+
+th.vfclass.v v4, v8
+# CHECK-INST: th.vfclass.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x88,0x8e]
+
+th.vfclass.v v4, v8, v0.t
+# CHECK-INST: th.vfclass.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x88,0x8c]
+
+th.vfmerge.vfm v4, v8, fa2, v0
+# CHECK-INST: th.vfmerge.vfm v4, v8, fa2, v0
+# CHECK-ENCODING: [0x57,0x52,0x86,0x5c]
+
+th.vfmv.v.f v4, fa1
+# CHECK-INST: th.vfmv.v.f v4, fa1
+# CHECK-ENCODING: [0x57,0xd2,0x05,0x5e]
+
+th.vfcvt.xu.f.v v4, v8
+# CHECK-INST: th.vfcvt.xu.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x80,0x8a]
+
+th.vfcvt.x.f.v v4, v8
+# CHECK-INST: th.vfcvt.x.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x92,0x80,0x8a]
+
+th.vfcvt.f.xu.v v4, v8
+# CHECK-INST: th.vfcvt.f.xu.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x81,0x8a]
+
+th.vfcvt.f.x.v v4, v8
+# CHECK-INST: th.vfcvt.f.x.v v4, v8
+# CHECK-ENCODING: [0x57,0x92,0x81,0x8a]
+
+th.vfcvt.xu.f.v v4, v8, v0.t
+# CHECK-INST: th.vfcvt.xu.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x80,0x88]
+
+th.vfcvt.x.f.v v4, v8, v0.t
+# CHECK-INST: th.vfcvt.x.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x92,0x80,0x88]
+
+th.vfcvt.f.xu.v v4, v8, v0.t
+# CHECK-INST: th.vfcvt.f.xu.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x81,0x88]
+
+th.vfcvt.f.x.v v4, v8, v0.t
+# CHECK-INST: th.vfcvt.f.x.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x92,0x81,0x88]
+
+th.vfwcvt.xu.f.v v4, v8
+# CHECK-INST: th.vfwcvt.xu.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x84,0x8a]
+
+th.vfwcvt.x.f.v v4, v8
+# CHECK-INST: th.vfwcvt.x.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x92,0x84,0x8a]
+
+th.vfwcvt.f.xu.v v4, v8
+# CHECK-INST: th.vfwcvt.f.xu.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x85,0x8a]
+
+th.vfwcvt.f.x.v v4, v8
+# CHECK-INST: th.vfwcvt.f.x.v v4, v8
+# CHECK-ENCODING: [0x57,0x92,0x85,0x8a]
+
+th.vfwcvt.f.f.v v4, v8
+# CHECK-INST: th.vfwcvt.f.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x86,0x8a]
+
+th.vfwcvt.xu.f.v v4, v8, v0.t
+# CHECK-INST: th.vfwcvt.xu.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x84,0x88]
+
+th.vfwcvt.x.f.v v4, v8, v0.t
+# CHECK-INST: th.vfwcvt.x.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x92,0x84,0x88]
+
+th.vfwcvt.f.xu.v v4, v8, v0.t
+# CHECK-INST: th.vfwcvt.f.xu.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x85,0x88]
+
+th.vfwcvt.f.x.v v4, v8, v0.t
+# CHECK-INST: th.vfwcvt.f.x.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x92,0x85,0x88]
+
+th.vfwcvt.f.f.v v4, v8, v0.t
+# CHECK-INST: th.vfwcvt.f.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x88]
+
+th.vfncvt.xu.f.v v4, v8
+# CHECK-INST: th.vfncvt.xu.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x88,0x8a]
+
+th.vfncvt.x.f.v v4, v8
+# CHECK-INST: th.vfncvt.x.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x92,0x88,0x8a]
+
+th.vfncvt.f.xu.v v4, v8
+# CHECK-INST: th.vfncvt.f.xu.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x89,0x8a]
+
+th.vfncvt.f.x.v v4, v8
+# CHECK-INST: th.vfncvt.f.x.v v4, v8
+# CHECK-ENCODING: [0x57,0x92,0x89,0x8a]
+
+th.vfncvt.f.f.v v4, v8
+# CHECK-INST: th.vfncvt.f.f.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x8a,0x8a]
+
+th.vfncvt.xu.f.v v4, v8, v0.t
+# CHECK-INST: th.vfncvt.xu.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x88,0x88]
+
+th.vfncvt.x.f.v v4, v8, v0.t
+# CHECK-INST: th.vfncvt.x.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x92,0x88,0x88]
+
+th.vfncvt.f.xu.v v4, v8, v0.t
+# CHECK-INST: th.vfncvt.f.xu.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x89,0x88]
+
+th.vfncvt.f.x.v v4, v8, v0.t
+# CHECK-INST: th.vfncvt.f.x.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x92,0x89,0x88]
+
+th.vfncvt.f.f.v v4, v8, v0.t
+# CHECK-INST: th.vfncvt.f.f.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x8a,0x88]
+
+th.vredsum.vs v4, v8, v12
+# CHECK-INST: th.vredsum.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x02]
+
+th.vredmaxu.vs v4, v8, v8
+# CHECK-INST: th.vredmaxu.vs v4, v8, v8
+# CHECK-ENCODING: [0x57,0x22,0x84,0x1a]
+
+th.vredmax.vs v4, v8, v8
+# CHECK-INST: th.vredmax.vs v4, v8, v8
+# CHECK-ENCODING: [0x57,0x22,0x84,0x1e]
+
+th.vredminu.vs v4, v8, v8
+# CHECK-INST: th.vredminu.vs v4, v8, v8
+# CHECK-ENCODING: [0x57,0x22,0x84,0x12]
+
+th.vredmin.vs v4, v8, v8
+# CHECK-INST: th.vredmin.vs v4, v8, v8
+# CHECK-ENCODING: [0x57,0x22,0x84,0x16]
+
+th.vredand.vs v4, v8, v12
+# CHECK-INST: th.vredand.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x06]
+
+th.vredor.vs v4, v8, v12
+# CHECK-INST: th.vredor.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x0a]
+
+th.vredxor.vs v4, v8, v12
+# CHECK-INST: th.vredxor.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x0e]
+
+th.vredsum.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vredsum.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x00]
+
+th.vredmaxu.vs v4, v8, v8, v0.t
+# CHECK-INST: th.vredmaxu.vs v4, v8, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x84,0x18]
+
+th.vredmax.vs v4, v8, v8, v0.t
+# CHECK-INST: th.vredmax.vs v4, v8, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x84,0x1c]
+
+th.vredminu.vs v4, v8, v8, v0.t
+# CHECK-INST: th.vredminu.vs v4, v8, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x84,0x10]
+
+th.vredmin.vs v4, v8, v8, v0.t
+# CHECK-INST: th.vredmin.vs v4, v8, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x84,0x14]
+
+th.vredand.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vredand.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x04]
+
+th.vredor.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vredor.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x08]
+
+th.vredxor.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vredxor.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x86,0x0c]
+
+th.vwredsumu.vs v4, v8, v12
+# CHECK-INST: th.vwredsumu.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xc2]
+
+th.vwredsum.vs v4, v8, v12
+# CHECK-INST: th.vwredsum.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0xc6]
+
+th.vwredsumu.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vwredsumu.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xc0]
+
+th.vwredsum.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vwredsum.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0xc4]
+
+th.vfredosum.vs v4, v8, v12
+# CHECK-INST: th.vfredosum.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x0e]
+
+th.vfredsum.vs v4, v8, v12
+# CHECK-INST: th.vfredsum.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x06]
+
+th.vfredmax.vs v4, v8, v12
+# CHECK-INST: th.vfredmax.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x1e]
+
+th.vfredmin.vs v4, v8, v12
+# CHECK-INST: th.vfredmin.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0x16]
+
+th.vfredosum.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vfredosum.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x0c]
+
+th.vfredsum.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vfredsum.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x04]
+
+th.vfredmax.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vfredmax.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x1c]
+
+th.vfredmin.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vfredmin.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0x14]
+
+th.vfwredosum.vs v4, v8, v12
+# CHECK-INST: th.vfwredosum.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0xce]
+
+th.vfwredsum.vs v4, v8, v12
+# CHECK-INST: th.vfwredsum.vs v4, v8, v12
+# CHECK-ENCODING: [0x57,0x12,0x86,0xc6]
+
+th.vfwredosum.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vfwredosum.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xcc]
+
+th.vfwredsum.vs v4, v8, v12, v0.t
+# CHECK-INST: th.vfwredsum.vs v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x86,0xc4]
+
+th.vmcpy.m v4, v8
+# CHECK-INST: th.vmcpy.m v4, v8
+# CHECK-ENCODING: [0x57,0x22,0x84,0x66]
+
+th.vmclr.m v4
+# CHECK-INST: th.vmclr.m v4
+# CHECK-ENCODING: [0x57,0x22,0x42,0x6e]
+
+th.vmset.m v4
+# CHECK-INST: th.vmset.m v4
+# CHECK-ENCODING: [0x57,0x22,0x42,0x7e]
+
+th.vmnot.m v4, v8
+# CHECK-INST: th.vmnot.m v4, v8
+# CHECK-ENCODING: [0x57,0x22,0x84,0x76]
+
+th.vmand.mm v4, v8, v12
+# CHECK-INST: th.vmand.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x66]
+
+th.vmnand.mm v4, v8, v12
+# CHECK-INST: th.vmnand.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x76]
+
+th.vmandnot.mm v4, v8, v12
+# CHECK-INST: th.vmandnot.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x62]
+
+th.vmxor.mm v4, v8, v12
+# CHECK-INST: th.vmxor.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x6e]
+
+th.vmor.mm v4, v8, v12
+# CHECK-INST: th.vmor.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x6a]
+
+th.vmnor.mm v4, v8, v12
+# CHECK-INST: th.vmnor.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x7a]
+
+th.vmornot.mm v4, v8, v12
+# CHECK-INST: th.vmornot.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x72]
+
+th.vmxnor.mm v4, v8, v12
+# CHECK-INST: th.vmxnor.mm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x7e]
+
+th.vmpopc.m a0, v12
+# CHECK-INST: th.vmpopc.m a0, v12
+# CHECK-ENCODING: [0x57,0x25,0xc0,0x52]
+
+th.vmfirst.m a0, v12
+# CHECK-INST: th.vmfirst.m a0, v12
+# CHECK-ENCODING: [0x57,0x25,0xc0,0x56]
+
+th.vmsbf.m v4, v8
+# CHECK-INST: th.vmsbf.m v4, v8
+# CHECK-ENCODING: [0x57,0xa2,0x80,0x5a]
+
+th.vmsif.m v4, v8
+# CHECK-INST: th.vmsif.m v4, v8
+# CHECK-ENCODING: [0x57,0xa2,0x81,0x5a]
+
+th.vmsof.m v4, v8
+# CHECK-INST: th.vmsof.m v4, v8
+# CHECK-ENCODING: [0x57,0x22,0x81,0x5a]
+
+th.viota.m v4, v8
+# CHECK-INST: th.viota.m v4, v8
+# CHECK-ENCODING: [0x57,0x22,0x88,0x5a]
+
+th.vid.v v4
+# CHECK-INST: th.vid.v v4
+# CHECK-ENCODING: [0x57,0xa2,0x08,0x5a]
+
+th.vmpopc.m a0, v12, v0.t
+# CHECK-INST: th.vmpopc.m a0, v12, v0.t
+# CHECK-ENCODING: [0x57,0x25,0xc0,0x50]
+
+th.vmfirst.m a0, v12, v0.t
+# CHECK-INST: th.vmfirst.m a0, v12, v0.t
+# CHECK-ENCODING: [0x57,0x25,0xc0,0x54]
+
+th.vmsbf.m v4, v8, v0.t
+# CHECK-INST: th.vmsbf.m v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0xa2,0x80,0x58]
+
+th.vmsif.m v4, v8, v0.t
+# CHECK-INST: th.vmsif.m v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0xa2,0x81,0x58]
+
+th.vmsof.m v4, v8, v0.t
+# CHECK-INST: th.vmsof.m v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x81,0x58]
+
+th.viota.m v4, v8, v0.t
+# CHECK-INST: th.viota.m v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x22,0x88,0x58]
+
+th.vid.v v4, v0.t
+# CHECK-INST: th.vid.v v4, v0.t
+# CHECK-ENCODING: [0x57,0xa2,0x08,0x58]
+
+th.vmv.x.s a0, v12
+# CHECK-INST: th.vmv.x.s a0, v12
+# CHECK-ENCODING: [0x57,0x25,0xc0,0x32]
+
+th.vext.x.v a0, v12, a2
+# CHECK-INST: th.vext.x.v a0, v12, a2
+# CHECK-ENCODING: [0x57,0x25,0xc6,0x32]
+
+th.vmv.s.x v4, a0
+# CHECK-INST: th.vmv.s.x v4, a0
+# CHECK-ENCODING: [0x57,0x62,0x05,0x36]
+
+th.vfmv.f.s fa0, v8
+# CHECK-INST: th.vfmv.f.s fa0, v8
+# CHECK-ENCODING: [0x57,0x15,0x80,0x32]
+
+th.vfmv.s.f v4, fa1
+# CHECK-INST: th.vfmv.s.f v4, fa1
+# CHECK-ENCODING: [0x57,0xd2,0x05,0x36]
+
+th.vslideup.vx v4, v8, a1
+# CHECK-INST: th.vslideup.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x3a]
+
+th.vslideup.vi v4, v8, 0
+# CHECK-INST: th.vslideup.vi v4, v8, 0
+# CHECK-ENCODING: [0x57,0x32,0x80,0x3a]
+
+th.vslideup.vi v4, v8, 31
+# CHECK-INST: th.vslideup.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x3a]
+
+th.vslidedown.vx v4, v8, a1
+# CHECK-INST: th.vslidedown.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x3e]
+
+th.vslidedown.vi v4, v8, 0
+# CHECK-INST: th.vslidedown.vi v4, v8, 0
+# CHECK-ENCODING: [0x57,0x32,0x80,0x3e]
+
+th.vslidedown.vi v4, v8, 31
+# CHECK-INST: th.vslidedown.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x3e]
+
+th.vslideup.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vslideup.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x38]
+
+th.vslideup.vi v4, v8, 0, v0.t
+# CHECK-INST: th.vslideup.vi v4, v8, 0, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x80,0x38]
+
+th.vslideup.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vslideup.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x38]
+
+th.vslidedown.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vslidedown.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x3c]
+
+th.vslidedown.vi v4, v8, 0, v0.t
+# CHECK-INST: th.vslidedown.vi v4, v8, 0, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x80,0x3c]
+
+th.vslidedown.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vslidedown.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x3c]
+
+th.vslide1up.vx v4, v8, a1
+# CHECK-INST: th.vslide1up.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x3a]
+
+th.vslide1down.vx v4, v8, a1
+# CHECK-INST: th.vslide1down.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x3e]
+
+th.vslide1up.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vslide1up.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x38]
+
+th.vslide1down.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vslide1down.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xe2,0x85,0x3c]
+
+th.vrgather.vv v4, v8, v12
+# CHECK-INST: th.vrgather.vv v4, v8, v12
+# CHECK-ENCODING: [0x57,0x02,0x86,0x32]
+
+th.vrgather.vx v4, v8, a1
+# CHECK-INST: th.vrgather.vx v4, v8, a1
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x32]
+
+th.vrgather.vi v4, v8, 0
+# CHECK-INST: th.vrgather.vi v4, v8, 0
+# CHECK-ENCODING: [0x57,0x32,0x80,0x32]
+
+th.vrgather.vi v4, v8, 31
+# CHECK-INST: th.vrgather.vi v4, v8, 31
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x32]
+
+th.vrgather.vv v4, v8, v12, v0.t
+# CHECK-INST: th.vrgather.vv v4, v8, v12, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x86,0x30]
+
+th.vrgather.vx v4, v8, a1, v0.t
+# CHECK-INST: th.vrgather.vx v4, v8, a1, v0.t
+# CHECK-ENCODING: [0x57,0xc2,0x85,0x30]
+
+th.vrgather.vi v4, v8, 0, v0.t
+# CHECK-INST: th.vrgather.vi v4, v8, 0, v0.t
+# CHECK-ENCODING: [0x57,0x32,0x80,0x30]
+
+th.vrgather.vi v4, v8, 31, v0.t
+# CHECK-INST: th.vrgather.vi v4, v8, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb2,0x8f,0x30]
+
+th.vcompress.vm v4, v8, v12
+# CHECK-INST: th.vcompress.vm v4, v8, v12
+# CHECK-ENCODING: [0x57,0x22,0x86,0x5e]
+
+csrr a0, vstart
+# CHECK-INST: csrr a0, vstart
+# CHECK-ENCODING: [0x73,0x25,0x80,0x00]
+
+csrr a0, vxsat
+# CHECK-INST: csrr a0, vxsat
+# CHECK-ENCODING: [0x73,0x25,0x90,0x00]
+
+csrr a0, vxrm
+# CHECK-INST: csrr a0, vxrm
+# CHECK-ENCODING: [0x73,0x25,0xa0,0x00]
+
+csrr a0, vl
+# CHECK-INST: csrr a0, vl
+# CHECK-ENCODING: [0x73,0x25,0x00,0xc2]
+
+csrr a0, vtype
+# CHECK-INST: csrr a0, vtype
+# CHECK-ENCODING: [0x73,0x25,0x10,0xc2]
>From 01694f94c5bc78d81cbfb3520bcc37d278ca9e4b Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Fri, 8 Mar 2024 16:05:47 +0800
Subject: [PATCH 5/9] fix unit test
---
llvm/unittests/Support/RISCVISAInfoTest.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 1ae0097b2efc87..ce5fad171a5dba 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -888,6 +888,8 @@ R"(All available -march extensions for RISC-V
xtheadmempair 1.0
xtheadsync 1.0
xtheadvdot 1.0
+ xtheadvector 1.0
+ xtheadzvamo 1.0
xventanacondops 1.0
Experimental extensions
>From ef30804bff893d3ac65e250580f6675f245d1d48 Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Fri, 8 Mar 2024 16:26:30 +0800
Subject: [PATCH 6/9] rename some old names
---
.../RISCV/Disassembler/RISCVDisassembler.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 +-
.../lib/Target/RISCV/RISCVInstrInfoXTHeadV.td | 48 +++++++++----------
3 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index a1ece2e3e58d4e..656bd5aac47ea5 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -581,7 +581,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"XTHeadSync custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
"XTHeadVdot custom opcode table");
- TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV, DecoderTableRVV0p7132,
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV, DecoderTableXTHeadVector32,
"XTHeadVector custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custom opcode table");
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 11e97007e7186a..51f5dd9597959f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1242,9 +1242,9 @@ def HasForcedSWShadowStack : Predicate<"Subtarget->hasForcedSWShadowStack()">;
//===----------------------------------------------------------------------===//
def FeatureVendorXTHeadV
- : SubtargetFeature<"xtheadvector", "HasVendorXTHeadV", "true",
+ : SubtargetFeature<"xtheadvector", "HasVendorXTHeadVector", "true",
"'xtheadvector' (T-Head Base Vector Instructions)">;
-def HasVendorXTHeadV : Predicate<"Subtarget->hasVendorXTHeadV()">,
+def HasVendorXTHeadVector : Predicate<"Subtarget->HasVendorXTHeadVector()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadV),
"'xtheadvector' (T-Head Base Vector Instructions)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
index 70905a589a06e1..9bb64c4ca7b000 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
@@ -258,8 +258,8 @@ multiclass TH_VAMO<bits<5> amoop, bits<3> width, string opcodestr> {
// Instructions
//===----------------------------------------------------------------------===//
-let DecoderNamespace = "RVV0p71" in {
-let Predicates = [HasVendorXTHeadV] in {
+let DecoderNamespace = "XTHeadVector" in {
+let Predicates = [HasVendorXTHeadVector] in {
// Configuration-Setting Instructions
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
def TH_VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, XTHeadVTypeI:$vtypei),
@@ -321,10 +321,10 @@ def TH_VLBUFF_V : TH_VLxUFF<0b000, 0b000, "th.vlbuff.v">;
def TH_VLHUFF_V : TH_VLxUFF<0b000, 0b101, "th.vlhuff.v">;
def TH_VLWUFF_V : TH_VLxUFF<0b000, 0b110, "th.vlwuff.v">;
def TH_VLEFF_V : TH_VLxUFF<0b000, 0b111, "th.vleff.v">;
-} // Predicates = [HasVendorXTHeadV]
+} // Predicates = [HasVendorXTHeadVector]
// The extension `Zvlsseg (chapter 7.8)` is not a subextension but a mandatory part of `XTheadVector`.
-let Predicates = [HasVendorXTHeadV] in {
+let Predicates = [HasVendorXTHeadVector] in {
foreach nf=2-8 in {
// Vector Unit-Stride Segment Loads and Stores
def TH_VLSEG#nf#B_V : TH_VLx<!add(nf, -1), 0b000, "th.vlseg"#nf#"b.v">;
@@ -372,10 +372,10 @@ foreach nf=2-8 in {
def TH_VSXSEG#nf#W_V : TH_VSXx<!add(nf, -1), 0b110, "th.vsxseg"#nf#"w.v">;
def TH_VSXSEG#nf#E_V : TH_VSXx<!add(nf, -1), 0b111, "th.vsxseg"#nf#"e.v">;
}
-} // Predicates = [HasVendorXTHeadV]
+} // Predicates = [HasVendorXTHeadVector]
// The extension `Zvamo` is renamed to `XTheadZvamo`.
-let Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA] in {
+let Predicates = [HasVendorXTHeadVector, HasVendorXTHeadZvamo, HasStdExtA] in {
// Vector AMO Instruction
defm TH_VAMOSWAPW : TH_VAMO<0b00001, 0b110, "th.vamoswapw.v">;
defm TH_VAMOADDW : TH_VAMO<0b00000, 0b110, "th.vamoaddw.v">;
@@ -406,9 +406,9 @@ let Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA] in {
defm TH_VAMOMAXQ : TH_VAMO<0b10100, 0b000, "th.vamomaxq.v">;
defm TH_VAMOMINUQ : TH_VAMO<0b11000, 0b000, "th.vamominuq.v">;
defm TH_VAMOMAXUQ : TH_VAMO<0b11100, 0b000, "th.vamomaxuq.v">;
-} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA]
+} // Predicates = [HasVendorXTHeadVector, HasVendorXTHeadZvamo, HasStdExtA]
-let Predicates = [HasVendorXTHeadV] in {
+let Predicates = [HasVendorXTHeadVector] in {
// Vector Single-Width Integer Add and Subtract
defm TH_VADD_V : VALU_IV_V_X_I<"th.vadd", 0b000000>;
defm TH_VSUB_V : VALU_IV_V_X<"th.vsub", 0b000010>;
@@ -565,9 +565,9 @@ let Constraints = "@earlyclobber $vd" in {
defm TH_VNCLIPU_W : TH_VNCLP_IV_V_X_I<"th.vnclipu", 0b101110>;
defm TH_VNCLIP_W : TH_VNCLP_IV_V_X_I<"th.vnclip", 0b101111>;
} // Constraints = "@earlyclobber $vd"
-} // Predicates = [HasVendorXTHeadV]
+} // Predicates = [HasVendorXTHeadVector]
-let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
+let Predicates = [HasVendorXTHeadVector, HasStdExtF] in {
// Vector Single-Width Floating-Point Add/Subtract Instructions
let Uses = [FRM], mayRaiseFPException = true in {
defm TH_VFADD_V : VALU_FV_V_F<"th.vfadd", 0b000000>;
@@ -707,9 +707,9 @@ defm TH_VFNCVT_F_X_W : VNCVTF_IV_VS2<"th.vfncvt.f.x.v", 0b100010, 0b10011>;
defm TH_VFNCVT_F_F_W : VNCVTF_FV_VS2<"th.vfncvt.f.f.v", 0b100010, 0b10100>;
}
} // Constraints = "@earlyclobber $vd", mayRaiseFPException = true
-} // Predicates = [HasVendorXTHeadV, HasStdExtF]
+} // Predicates = [HasVendorXTHeadVector, HasStdExtF]
-let Predicates = [HasVendorXTHeadV] in {
+let Predicates = [HasVendorXTHeadVector] in {
// Vector Single-Width Integer Reduction Instructions
let RVVConstraint = NoConstraint in {
defm TH_VREDSUM : VRED_MV_V<"th.vredsum", 0b000000>;
@@ -732,9 +732,9 @@ defm TH_VWREDSUMU : VWRED_IV_V<"th.vwredsumu", 0b110000>;
defm TH_VWREDSUM : VWRED_IV_V<"th.vwredsum", 0b110001>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
-} // Predicates = [HasVendorXTHeadV]
+} // Predicates = [HasVendorXTHeadVector]
-let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
+let Predicates = [HasVendorXTHeadVector, HasStdExtF] in {
// Vector Single-Width Floating-Point Reduction Instructions
let RVVConstraint = NoConstraint in {
let Uses = [FRM], mayRaiseFPException = true in {
@@ -758,9 +758,9 @@ defm TH_VFWREDOSUM : VWREDO_FV_V<"th.vfwredosum", 0b110011>;
defm TH_VFWREDUSUM : VWRED_FV_V<"th.vfwredsum", 0b110001>;
}
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
-} // Predicates = [HasVendorXTHeadV, HasStdExtF]
+} // Predicates = [HasVendorXTHeadVector, HasStdExtF]
-let Predicates = [HasVendorXTHeadV] in {
+let Predicates = [HasVendorXTHeadVector] in {
// Vector Mask-Register Logical Instructions
let RVVConstraint = NoConstraint in {
defm TH_VMAND_M : VMALU_MV_Mask<"th.vmand", 0b011001, "m">;
@@ -828,9 +828,9 @@ def TH_VMV_S_X : RVInstV2<0b001101, 0b00000, OPMVX, (outs VR:$vd_wb),
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
-} // Predicates = [HasVendorXTHeadV]
+} // Predicates = [HasVendorXTHeadVector]
-let Predicates = [HasVendorXTHeadV, HasStdExtF] in {
+let Predicates = [HasVendorXTHeadVector, HasStdExtF] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
RVVConstraint = NoConstraint in {
// Floating-Point Scalar Move Instructions
@@ -845,9 +845,9 @@ def TH_VFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb),
Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
-} // Predicates = [HasVendorXTHeadV, HasStdExtF]
+} // Predicates = [HasVendorXTHeadVector, HasStdExtF]
-let Predicates = [HasVendorXTHeadV] in {
+let Predicates = [HasVendorXTHeadVector] in {
// Vector Slide Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
defm TH_VSLIDEUP_V : VSLD_IV_X_I<"th.vslideup", 0b001110>;
@@ -865,11 +865,11 @@ defm TH_VRGATHER_V : VGTR_IV_V_X_I<"th.vrgather", 0b001100>;
let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
defm TH_VCOMPRESS_V : VCPR_MV_Mask<"th.vcompress", 0b010111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
-} // Predicates = [HasVendorXTHeadV]
-} // DecoderNamespace = "RVV0p71"
+} // Predicates = [HasVendorXTHeadVector]
+} // DecoderNamespace = "XTHeadVector"
// Pseudo instructions
-let Predicates = [HasVendorXTHeadV] in {
+let Predicates = [HasVendorXTHeadVector] in {
// Vector Integer Comparison Instructions
def : InstAlias<"th.vmsgtu.vv $vd, $va, $vb$vm",
(TH_VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
@@ -964,4 +964,4 @@ def : InstAlias<"th.vmset.m $vd",
def : InstAlias<"th.vmnot.m $vd, $vs",
(TH_VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>;
-} // Predicates = [HasVendorXTHeadV]
+} // Predicates = [HasVendorXTHeadVector]
>From 4473f82c5bb9461c043c0eaee2eb7efc79aaaa9f Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Fri, 8 Mar 2024 17:09:32 +0800
Subject: [PATCH 7/9] clang format
---
llvm/lib/Support/RISCVISAInfo.cpp | 6 ++--
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 28 +++++++++++--------
.../RISCV/Disassembler/RISCVDisassembler.cpp | 3 +-
llvm/lib/TargetParser/RISCVTargetParser.cpp | 3 +-
4 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index f8f8b152c20eca..692a0086d9a28c 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -1055,9 +1055,9 @@ Error RISCVISAInfo::checkDependency() {
"'xtheadzvamo' requires 'a' extension to also be specified");
if (Exts.count("xtheadvector") && HasVector)
- return createStringError(
- errc::invalid_argument,
- "'xtheadvector' extension is incompatible with 'v' or 'zve*' extension");
+ return createStringError(errc::invalid_argument,
+ "'xtheadvector' extension is incompatible with "
+ "'v' or 'zve*' extension");
return Error::success();
}
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 32d08cfeafe2cd..41329aee8c7c39 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -168,7 +168,8 @@ class RISCVAsmParser : public MCTargetAsmParser {
SMLoc IDLoc, MCStreamer &Out, bool IsSigned);
// Helper to emit pseudo vmsge{u}.vx instruction for XTHeadV extension.
- void emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, MCStreamer &Out);
+ void emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
+ MCStreamer &Out);
// Checks that a PseudoAddTPRel is using x4/tp in its second input operand.
// Enforcing this using a restricted register class for the second input
@@ -1189,7 +1190,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<RISCVOperand> createXTHeadVType(unsigned VTypeI, SMLoc S) {
+ static std::unique_ptr<RISCVOperand> createXTHeadVType(unsigned VTypeI,
+ SMLoc S) {
auto Op = std::make_unique<RISCVOperand>(KindTy::XTHeadVType);
Op->VType.Val = VTypeI;
Op->StartLoc = S;
@@ -1623,10 +1625,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
}
case Match_InvalidXTHeadVTypeI: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
- return Error(
- ErrorLoc,
- "operand must be "
- "e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|8] for XTHeadVector");
+ return Error(ErrorLoc, "operand must be "
+ "e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|"
+ "8] for XTHeadVector");
}
case Match_InvalidVMaskRegister: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
@@ -3426,7 +3427,6 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
}
}
-
void RISCVAsmParser::emitVMSGE_VI(MCInst &Inst, unsigned Opcode,
unsigned OpcodeImmIs0, SMLoc IDLoc,
MCStreamer &Out, bool IsSigned) {
@@ -3461,7 +3461,7 @@ void RISCVAsmParser::emitVMSGE_VI(MCInst &Inst, unsigned Opcode,
}
void RISCVAsmParser::emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
- MCStreamer &Out) {
+ MCStreamer &Out) {
// https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1
if (Inst.getNumOperands() == 3) {
// unmasked va >= x
@@ -3825,16 +3825,20 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
emitVMSGE_TH(Inst, RISCV::TH_VMSLT_VX, IDLoc, Out);
return false;
case RISCV::PseudoTH_VMSGE_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSGT_VI, RISCV::TH_VMSGT_VI, IDLoc, Out, true);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSGT_VI, RISCV::TH_VMSGT_VI, IDLoc, Out,
+ true);
return false;
case RISCV::PseudoTH_VMSLT_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSLE_VI, RISCV::TH_VMSLE_VI, IDLoc, Out, true);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSLE_VI, RISCV::TH_VMSLE_VI, IDLoc, Out,
+ true);
return false;
case RISCV::PseudoTH_VMSGEU_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSGTU_VI, RISCV::TH_VMSEQ_VV, IDLoc, Out, false);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSGTU_VI, RISCV::TH_VMSEQ_VV, IDLoc, Out,
+ false);
return false;
case RISCV::PseudoTH_VMSLTU_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSLEU_VI, RISCV::TH_VMSNE_VV, IDLoc, Out, false);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSLEU_VI, RISCV::TH_VMSNE_VV, IDLoc, Out,
+ false);
return false;
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 656bd5aac47ea5..697ae03bd310bb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -581,7 +581,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"XTHeadSync custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
"XTHeadVdot custom opcode table");
- TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV, DecoderTableXTHeadVector32,
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV,
+ DecoderTableXTHeadVector32,
"XTHeadVector custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custom opcode table");
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 1a10b572bebdbe..cb17c1ea31187c 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -153,8 +153,7 @@ unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
// 6:5 | vediv[1:0] | Used by EDIV extension
// 4:2 | vsew[2:0] | Standard element width (SEW) setting
// 1:0 | vlmul[1:0] | Vector register group multiplier (LMUL) setting
-unsigned encodeXTHeadVTYPE(unsigned SEW, unsigned LMUL,
- unsigned EDIV) {
+unsigned encodeXTHeadVTYPE(unsigned SEW, unsigned LMUL, unsigned EDIV) {
unsigned VSEWBits = encodeSEW(SEW);
unsigned VLMULBits = encodeLMUL(LMUL, false);
unsigned VEDIVBits = encodeEDIV(EDIV);
>From 4fd95992fa845a9be4d6cb179915d898ae6a45a4 Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Fri, 8 Mar 2024 17:28:34 +0800
Subject: [PATCH 8/9] add 5 assembly pseudoinstructions for XTheadVector
extension.
Reference: https://github.com/T-head-Semi/thead-extension-spec/commit/2420d05a39bd2901e65822386ce2cbb75fb5dc16
---
.../lib/Target/RISCV/RISCVInstrInfoXTHeadV.td | 27 +++++++++++++++++--
.../RISCV/xtheadvector/xtheadvector-pseudos.s | 26 ++++++++++++++++++
2 files changed, 51 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/MC/RISCV/xtheadvector/xtheadvector-pseudos.s
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
index 9bb64c4ca7b000..ef2e948e7f7a4a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
@@ -464,8 +464,8 @@ defm TH_VSRA_V : VSHT_IV_V_X_I<"th.vsra", 0b101001>;
// vector register group (specified by vs2). The destination vector register
// group cannot overlap the mask register if used, unless LMUL=1.
let Constraints = "@earlyclobber $vd" in {
-defm TH_VNSRL_W : TH_VNSHT_IV_V_X_I<"th.vnsrl", 0b101100>;
-defm TH_VNSRA_W : TH_VNSHT_IV_V_X_I<"th.vnsra", 0b101101>;
+defm TH_VNSRL_V : TH_VNSHT_IV_V_X_I<"th.vnsrl", 0b101100>;
+defm TH_VNSRA_V : TH_VNSHT_IV_V_X_I<"th.vnsra", 0b101101>;
} // Constraints = "@earlyclobber $vd"
// Vector Integer Comparison Instructions
@@ -964,4 +964,27 @@ def : InstAlias<"th.vmset.m $vd",
def : InstAlias<"th.vmnot.m $vd, $vs",
(TH_VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>;
+// From XTHeadVector spec:
+// https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadvector.adoc
+// Beyond the instructions and pseudo instructions in the referenced specification,
+// the following additional pseudo instructions are defined in order to improve compatibility with RVV 1.0:
+// th.vmmv.m vd,v => th.vmand.mm vd,vs,vs
+// th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0
+// th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm
+// th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs
+// th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs
+
+// Note: DO NOT "Emit" `th.vmmv.m` (the 0 for the third argument) in printed assembly.
+// As `th.vmcpy.m` also expands to `th.vmand.mm`, we need clarification from T-Head.
+def : InstAlias<"th.vmmv.m $vd, $vs",
+ (TH_VMAND_MM VR:$vd, VR:$vs, VR:$vs), 0>;
+def : InstAlias<"th.vneg.v $vd, $vs",
+ (TH_VRSUB_VX VR:$vd, VR:$vs, X0, zero_reg)>;
+def : InstAlias<"th.vncvt.x.x.v $vd, $vs$vm",
+ (TH_VNSRL_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
+def : InstAlias<"th.vfneg.v $vd, $vs",
+ (TH_VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>;
+def : InstAlias<"th.vfabs.v $vd, $vs",
+ (TH_VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>;
+
} // Predicates = [HasVendorXTHeadVector]
diff --git a/llvm/test/MC/RISCV/xtheadvector/xtheadvector-pseudos.s b/llvm/test/MC/RISCV/xtheadvector/xtheadvector-pseudos.s
new file mode 100644
index 00000000000000..618d4c37ac408b
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/xtheadvector-pseudos.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+f,+a,+xtheadvector,+xtheadzvamo %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+th.vmmv.m v4, v8
+# CHECK-INST: th.vmcpy.m v4, v8
+# CHECK-ENCODING: [0x57,0x22,0x84,0x66]
+
+th.vneg.v v4, v8
+# CHECK-INST: th.vneg.v v4, v8
+# CHECK-ENCODING: [0x57,0x42,0x80,0x0e]
+
+th.vncvt.x.x.v v4, v8
+# CHECK-INST: th.vnsrl.vx v4, v8, zero
+# CHECK-ENCODING: [0x57,0x42,0x80,0xb2]
+
+th.vncvt.x.x.v v4, v8, v0.t
+# CHECK-INST: th.vncvt.x.x.v v4, v8, v0.t
+# CHECK-ENCODING: [0x57,0x42,0x80,0xb0]
+
+th.vfneg.v v4, v8
+# CHECK-INST: th.vfneg.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x84,0x26]
+
+th.vfabs.v v4, v8
+# CHECK-INST: th.vfabs.v v4, v8
+# CHECK-ENCODING: [0x57,0x12,0x84,0x2a]
>From 2e05b9b7c5146dbe3cf84129fd0ffba6e0e29a4c Mon Sep 17 00:00:00 2001
From: kata-ark <zengtao at iscas.ac.cn>
Date: Fri, 8 Mar 2024 17:29:00 +0800
Subject: [PATCH 9/9] add tests about `th.vmsge.vx`
---
llvm/test/MC/RISCV/xtheadvector/invalid.s | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 llvm/test/MC/RISCV/xtheadvector/invalid.s
diff --git a/llvm/test/MC/RISCV/xtheadvector/invalid.s b/llvm/test/MC/RISCV/xtheadvector/invalid.s
new file mode 100644
index 00000000000000..573a3cfe37d1b3
--- /dev/null
+++ b/llvm/test/MC/RISCV/xtheadvector/invalid.s
@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+xtheadvector %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+
+th.vmsge.vx v2, v4, a0, v0.t, v0
+# CHECK-ERROR: invalid operand for instruction
+
+th.vmsgeu.vx v2, v4, a0, v0.t, v0
+# CHECK-ERROR: invalid operand for instruction
+
+th.vmsge.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
+
+th.vmsgeu.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
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