[llvm] [llvm][mc][riscv] MC support of T-Head vector extension (xtheadvector) (PR #84447)
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Fri Mar 8 00:49:43 PST 2024
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git-clang-format --diff ea23761429faa4e61d7a601da9a313dfdc058cb0 ef30804bff893d3ac65e250580f6675f245d1d48 -- llvm/include/llvm/TargetParser/RISCVTargetParser.h llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/TargetParser/RISCVTargetParser.cpp llvm/unittests/Support/RISCVISAInfoTest.cpp
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diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index f8f8b152c2..692a0086d9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -1055,9 +1055,9 @@ Error RISCVISAInfo::checkDependency() {
"'xtheadzvamo' requires 'a' extension to also be specified");
if (Exts.count("xtheadvector") && HasVector)
- return createStringError(
- errc::invalid_argument,
- "'xtheadvector' extension is incompatible with 'v' or 'zve*' extension");
+ return createStringError(errc::invalid_argument,
+ "'xtheadvector' extension is incompatible with "
+ "'v' or 'zve*' extension");
return Error::success();
}
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 32d08cfeaf..41329aee8c 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -168,7 +168,8 @@ class RISCVAsmParser : public MCTargetAsmParser {
SMLoc IDLoc, MCStreamer &Out, bool IsSigned);
// Helper to emit pseudo vmsge{u}.vx instruction for XTHeadV extension.
- void emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, MCStreamer &Out);
+ void emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
+ MCStreamer &Out);
// Checks that a PseudoAddTPRel is using x4/tp in its second input operand.
// Enforcing this using a restricted register class for the second input
@@ -1189,7 +1190,8 @@ public:
return Op;
}
- static std::unique_ptr<RISCVOperand> createXTHeadVType(unsigned VTypeI, SMLoc S) {
+ static std::unique_ptr<RISCVOperand> createXTHeadVType(unsigned VTypeI,
+ SMLoc S) {
auto Op = std::make_unique<RISCVOperand>(KindTy::XTHeadVType);
Op->VType.Val = VTypeI;
Op->StartLoc = S;
@@ -1623,10 +1625,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
}
case Match_InvalidXTHeadVTypeI: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
- return Error(
- ErrorLoc,
- "operand must be "
- "e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|8] for XTHeadVector");
+ return Error(ErrorLoc, "operand must be "
+ "e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|"
+ "8] for XTHeadVector");
}
case Match_InvalidVMaskRegister: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
@@ -3426,7 +3427,6 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
}
}
-
void RISCVAsmParser::emitVMSGE_VI(MCInst &Inst, unsigned Opcode,
unsigned OpcodeImmIs0, SMLoc IDLoc,
MCStreamer &Out, bool IsSigned) {
@@ -3461,7 +3461,7 @@ void RISCVAsmParser::emitVMSGE_VI(MCInst &Inst, unsigned Opcode,
}
void RISCVAsmParser::emitVMSGE_TH(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
- MCStreamer &Out) {
+ MCStreamer &Out) {
// https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1
if (Inst.getNumOperands() == 3) {
// unmasked va >= x
@@ -3825,16 +3825,20 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
emitVMSGE_TH(Inst, RISCV::TH_VMSLT_VX, IDLoc, Out);
return false;
case RISCV::PseudoTH_VMSGE_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSGT_VI, RISCV::TH_VMSGT_VI, IDLoc, Out, true);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSGT_VI, RISCV::TH_VMSGT_VI, IDLoc, Out,
+ true);
return false;
case RISCV::PseudoTH_VMSLT_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSLE_VI, RISCV::TH_VMSLE_VI, IDLoc, Out, true);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSLE_VI, RISCV::TH_VMSLE_VI, IDLoc, Out,
+ true);
return false;
case RISCV::PseudoTH_VMSGEU_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSGTU_VI, RISCV::TH_VMSEQ_VV, IDLoc, Out, false);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSGTU_VI, RISCV::TH_VMSEQ_VV, IDLoc, Out,
+ false);
return false;
case RISCV::PseudoTH_VMSLTU_VI:
- emitVMSGE_VI(Inst, RISCV::TH_VMSLEU_VI, RISCV::TH_VMSNE_VV, IDLoc, Out, false);
+ emitVMSGE_VI(Inst, RISCV::TH_VMSLEU_VI, RISCV::TH_VMSNE_VV, IDLoc, Out,
+ false);
return false;
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 656bd5aac4..697ae03bd3 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -581,7 +581,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"XTHeadSync custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
"XTHeadVdot custom opcode table");
- TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV, DecoderTableXTHeadVector32,
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV,
+ DecoderTableXTHeadVector32,
"XTHeadVector custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custom opcode table");
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 1a10b572be..cb17c1ea31 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -153,8 +153,7 @@ unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
// 6:5 | vediv[1:0] | Used by EDIV extension
// 4:2 | vsew[2:0] | Standard element width (SEW) setting
// 1:0 | vlmul[1:0] | Vector register group multiplier (LMUL) setting
-unsigned encodeXTHeadVTYPE(unsigned SEW, unsigned LMUL,
- unsigned EDIV) {
+unsigned encodeXTHeadVTYPE(unsigned SEW, unsigned LMUL, unsigned EDIV) {
unsigned VSEWBits = encodeSEW(SEW);
unsigned VLMULBits = encodeLMUL(LMUL, false);
unsigned VEDIVBits = encodeEDIV(EDIV);
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https://github.com/llvm/llvm-project/pull/84447
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