[llvm] [CodeGen] Port selection dag isel to new pass manager (PR #83567)

[via llvm-commits]

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@@ -39,13 +41,22 @@ void X86CodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
   // TODO: Add AsmPrinter.
 }
 
-Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &) const {
+Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
   // TODO: Add instruction selector.
+  addPass(X86ISelDAGToDAGPass(static_cast<X86TargetMachine &>(TM)));
   return Error::success();
 }
 
 } // namespace
 
+void X86TargetMachine::registerPassBuilderCallbacks(
+    PassBuilder &PB, bool PopulateClassToPassNames) {
+  if (PopulateClassToPassNames) {
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paperchalice wrote:

Yes, each target should provide `<Target>PassRegistry.def`, like #70921.

https://github.com/llvm/llvm-project/pull/83567