[llvm] cc34e56 - [PPC][NFC] add an option to expose the bug in 74951
Chen Zheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 7 17:55:19 PST 2024
Author: Chen Zheng
Date: 2024-03-07T20:52:44-05:00
New Revision: cc34e56b865f1fc9e894b75fc958f09dff0fcdea
URL: https://github.com/llvm/llvm-project/commit/cc34e56b865f1fc9e894b75fc958f09dff0fcdea
DIFF: https://github.com/llvm/llvm-project/commit/cc34e56b865f1fc9e894b75fc958f09dff0fcdea.diff
LOG: [PPC][NFC] add an option to expose the bug in 74951
Added:
Modified:
llvm/test/CodeGen/PowerPC/pr74951.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/pr74951.ll b/llvm/test/CodeGen/PowerPC/pr74951.ll
index a0d19fc09cc276..c1b2e3ee0dd68b 100644
--- a/llvm/test/CodeGen/PowerPC/pr74951.ll
+++ b/llvm/test/CodeGen/PowerPC/pr74951.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
+; RUN: llc < %s -start-before=codegenprepare -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN: -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
%struct.anon = type { i32 }
@@ -11,26 +12,28 @@ define noundef signext i32 @main() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld r3, L..C0(r2) # @b
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r4, r3
-; CHECK-NEXT: neg r4, r4
-; CHECK-NEXT: andi. r5, r3, 65535
-; CHECK-NEXT: rldicl r4, r4, 1, 63
+; CHECK-NEXT: andi. r4, r3, 65535
; CHECK-NEXT: bne cr0, L..BB0_4
; CHECK-NEXT: # %bb.1: # %lor.rhs.i.i
-; CHECK-NEXT: xori r5, r4, 1
-; CHECK-NEXT: cmpw r3, r5
+; CHECK-NEXT: extsw r4, r3
+; CHECK-NEXT: neg r5, r4
+; CHECK-NEXT: rldicl r5, r5, 1, 63
+; CHECK-NEXT: xori r5, r5, 1
+; CHECK-NEXT: cmpw r4, r5
; CHECK-NEXT: crnot 4*cr5+lt, eq
-; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: li r4, 1
; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_3
; CHECK-NEXT: # %bb.2: # %lor.rhs.i.i
-; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r4, 0
; CHECK-NEXT: L..BB0_3: # %lor.rhs.i.i
; CHECK-NEXT: ld r5, L..C1(r2) # @g
-; CHECK-NEXT: stb r3, 0(r5)
+; CHECK-NEXT: stb r4, 0(r5)
; CHECK-NEXT: L..BB0_4: # %g.exit
-; CHECK-NEXT: ld r5, L..C1(r2) # @g
+; CHECK-NEXT: ld r4, L..C1(r2) # @g
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: rldicl r5, r3, 1, 63
; CHECK-NEXT: li r3, 0
-; CHECK-NEXT: stb r4, 0(r5)
+; CHECK-NEXT: stb r5, 0(r4)
; CHECK-NEXT: blr
entry:
%0 = load i32, ptr @b, align 4
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