[llvm] [Xtensa] Implement base CallConvention. (PR #83280)
Andrei Safronov via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 7 16:49:27 PST 2024
================
@@ -23,5 +24,73 @@
using namespace llvm;
+static inline const MachineInstrBuilder &
+addFrameReference(const MachineInstrBuilder &MIB, int FI) {
+ MachineInstr *MI = MIB;
+ MachineFunction &MF = *MI->getParent()->getParent();
+ MachineFrameInfo &MFFrame = MF.getFrameInfo();
+ const MCInstrDesc &MCID = MI->getDesc();
+ MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
+ if (MCID.mayLoad())
+ Flags |= MachineMemOperand::MOLoad;
+ if (MCID.mayStore())
+ Flags |= MachineMemOperand::MOStore;
+ int64_t Offset = 0;
+ Align Alignment = MFFrame.getObjectAlign(FI);
+
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI, Offset),
+ Flags, MFFrame.getObjectSize(FI), Alignment);
+ return MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
+}
+
XtensaInstrInfo::XtensaInstrInfo(const XtensaSubtarget &STI)
: XtensaGenInstrInfo(), RI(STI), STI(STI) {}
+
+void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, MCRegister DestReg,
+ MCRegister SrcReg, bool KillSrc) const {
+ // when we are copying a phys reg we want the bits for fp
+ if (Xtensa::ARRegClass.contains(DestReg, SrcReg))
+ BuildMI(MBB, MBBI, DL, get(Xtensa::OR), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ else
+ report_fatal_error("Impossible reg-to-reg copy");
+}
+
+void XtensaInstrInfo::storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIdx, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg) const {
+ DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+ unsigned LoadOpcode, StoreOpcode;
+ getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx);
+ addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
----------------
andreisfr wrote:
Corrected
https://github.com/llvm/llvm-project/pull/83280
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