[llvm] [CodeGen] Port selection dag isel to new pass manager (PR #83567)

[Arthur Eubanks via llvm-commits]

================
@@ -39,13 +41,22 @@ void X86CodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
   // TODO: Add AsmPrinter.
 }
 
-Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &) const {
+Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
   // TODO: Add instruction selector.
+  addPass(X86ISelDAGToDAGPass(static_cast<X86TargetMachine &>(TM)));
   return Error::success();
 }
 
 } // namespace
 
+void X86TargetMachine::registerPassBuilderCallbacks(
+    PassBuilder &PB, bool PopulateClassToPassNames) {
+  if (PopulateClassToPassNames) {
----------------
aeubanks wrote:

should we generalize the `PassRegistry.def` mechanism so each backend doesn't have to repeat code like 
```
  PB.registerPipelineParsingCallback(
      [](StringRef PassName, ModulePassManager &PM,
         ArrayRef<PassBuilder::PipelineElement>) {
        if (PassName == "print-dxil-resource") {
          PM.addPass(DXILResourcePrinterPass(dbgs()));
          return true;
        }
        if (PassName == "print-dx-shader-flags") {
          PM.addPass(dxil::ShaderFlagsAnalysisPrinter(dbgs()));
          return true;
        }
        return false;
      });
```
and can more easily populate class names?

https://github.com/llvm/llvm-project/pull/83567