[llvm] [RISCV] Split div vs rem scheduling information [nfc] (PR #84385)
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Thu Mar 7 13:48:27 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Philip Reames (preames)
<details>
<summary>Changes</summary>
Allows a processor to define different latencies for the two operations.
---
Full diff: https://github.com/llvm/llvm-project/pull/84385.diff
7 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoM.td (+4-4)
- (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+12)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+13)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td (+12)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td (+5-1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td (+5-1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+6-2)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
index 6b43d4393f7670..8ea1560e5b372e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
@@ -41,9 +41,9 @@ def DIV : ALU_rr<0b0000001, 0b100, "div">,
def DIVU : ALU_rr<0b0000001, 0b101, "divu">,
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
def REM : ALU_rr<0b0000001, 0b110, "rem">,
- Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
+ Sched<[WriteIRem, ReadIRem, ReadIRem]>;
def REMU : ALU_rr<0b0000001, 0b111, "remu">,
- Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
+ Sched<[WriteIRem, ReadIRem, ReadIRem]>;
} // Predicates = [HasStdExtM]
let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in {
@@ -57,9 +57,9 @@ def DIVW : ALUW_rr<0b0000001, 0b100, "divw">,
def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">,
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
def REMW : ALUW_rr<0b0000001, 0b110, "remw">,
- Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
+ Sched<[WriteIRem32, ReadIRem32, ReadIRem32]>;
def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
- Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
+ Sched<[WriteIRem32, ReadIRem32, ReadIRem32]>;
} // Predicates = [HasStdExtM, IsRV64]
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 60fa1a848306d8..e74c7aab7474da 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -77,6 +77,16 @@ def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
let ReleaseAtCycles = [33];
}
+// Integer remainder
+def : WriteRes<WriteIRem32, [RocketUnitIDiv]> {
+ let Latency = 34;
+ let ReleaseAtCycles = [34];
+}
+def : WriteRes<WriteIRem, [RocketUnitIDiv]> {
+ let Latency = 33;
+ let ReleaseAtCycles = [33];
+}
+
// Memory
def : WriteRes<WriteSTB, [RocketUnitMem]>;
def : WriteRes<WriteSTH, [RocketUnitMem]>;
@@ -189,6 +199,8 @@ def : ReadAdvance<ReadShiftReg, 0>;
def : ReadAdvance<ReadShiftReg32, 0>;
def : ReadAdvance<ReadIDiv, 0>;
def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
def : ReadAdvance<ReadIMul, 0>;
def : ReadAdvance<ReadIMul32, 0>;
def : ReadAdvance<ReadAtomicWA, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 0430d603620b6a..b21a56bdcdd20a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -189,6 +189,7 @@ class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>
WriteREV8, WriteORCB, WriteSFB,
WriteIMul, WriteIMul32,
WriteIDiv, WriteIDiv32,
+ WriteIRem, WriteIRem32,
WriteLDB, WriteLDH, WriteLDW, WriteLDD]>;
// SiFive7 machine model for scheduling and other instruction cost heuristics.
@@ -273,6 +274,16 @@ def : WriteRes<WriteIDiv32, [SiFive7PipeB, SiFive7IDiv]> {
let ReleaseAtCycles = [1, 33];
}
+// Integer remainder
+def : WriteRes<WriteIRem, [SiFive7PipeB, SiFive7IDiv]> {
+ let Latency = 66;
+ let ReleaseAtCycles = [1, 65];
+}
+def : WriteRes<WriteIRem32, [SiFive7PipeB, SiFive7IDiv]> {
+ let Latency = 34;
+ let ReleaseAtCycles = [1, 33];
+}
+
// Bitmanip
let Latency = 3 in {
// Rotates are in the late-B ALU.
@@ -946,6 +957,8 @@ def : SiFive7AnyToGPRBypass<ReadShiftReg>;
def : SiFive7AnyToGPRBypass<ReadShiftReg32>;
def : ReadAdvance<ReadIDiv, 0>;
def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
def : ReadAdvance<ReadIMul, 0>;
def : ReadAdvance<ReadIMul32, 0>;
def : ReadAdvance<ReadAtomicWA, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 01398dea14a3b9..d02d34a0fb9c58 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -86,6 +86,16 @@ def : WriteRes<WriteIDiv32, [SiFiveP400MulDiv, SiFiveP400Div]> {
let ReleaseAtCycles = [1, 19];
}
+// Integer remainder
+def : WriteRes<WriteIRem, [SiFiveP400MulDiv, SiFiveP400Div]> {
+ let Latency = 35;
+ let ReleaseAtCycles = [1, 34];
+}
+def : WriteRes<WriteIRem32, [SiFiveP400MulDiv, SiFiveP400Div]> {
+ let Latency = 20;
+ let ReleaseAtCycles = [1, 19];
+}
+
let Latency = 1 in {
// Bitmanip
def : WriteRes<WriteRotateImm, [SiFiveP400IntArith]>;
@@ -258,6 +268,8 @@ def : ReadAdvance<ReadShiftReg, 0>;
def : ReadAdvance<ReadShiftReg32, 0>;
def : ReadAdvance<ReadIDiv, 0>;
def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
def : ReadAdvance<ReadIMul, 0>;
def : ReadAdvance<ReadIMul32, 0>;
def : ReadAdvance<ReadAtomicWA, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
index f2c07810867bd2..9625d17e0b2600 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -54,10 +54,12 @@ def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
def : WriteRes<WriteIMul, [SCR1_MUL]>;
def : WriteRes<WriteIMul32, [SCR1_MUL]>;
-// Integer division: latency 33, inverse throughput 33
+// Integer division/remainder: latency 33, inverse throughput 33
let Latency = 33, ReleaseAtCycles = [33] in {
def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
def : WriteRes<WriteIDiv, [SCR1_DIV]>;
+def : WriteRes<WriteIRem32, [SCR1_DIV]>;
+def : WriteRes<WriteIRem, [SCR1_DIV]>;
}
// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
@@ -147,6 +149,8 @@ def : ReadAdvance<ReadShiftReg, 0>;
def : ReadAdvance<ReadShiftReg32, 0>;
def : ReadAdvance<ReadIDiv, 0>;
def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
def : ReadAdvance<ReadIMul, 0>;
def : ReadAdvance<ReadIMul32, 0>;
def : ReadAdvance<ReadAtomicWA, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
index 667b5983cb401c..ef491edf3671f8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
@@ -64,11 +64,13 @@ def : WriteRes<WriteIMul, [XS2MDU]>;
def : WriteRes<WriteIMul32, [XS2MDU]>;
}
-// Integer division
+// Integer division/remainder
// SRT16 algorithm
let Latency = 20, ReleaseAtCycles = [20] in {
def : WriteRes<WriteIDiv32, [XS2MDU]>;
def : WriteRes<WriteIDiv, [XS2MDU]>;
+def : WriteRes<WriteIRem32, [XS2MDU]>;
+def : WriteRes<WriteIRem, [XS2MDU]>;
}
// Zb*
@@ -221,6 +223,8 @@ def : XS2LoadToALUBypass<ReadShiftReg>;
def : XS2LoadToALUBypass<ReadShiftReg32>;
def : ReadAdvance<ReadIDiv, 0>;
def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
def : ReadAdvance<ReadIMul, 0>;
def : ReadAdvance<ReadIMul32, 0>;
def : ReadAdvance<ReadAtomicWA, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
index 593921bfcc67ab..1d19624342d2bb 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -13,8 +13,10 @@ def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operatio
def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
-def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
-def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
+def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
+def WriteIDiv32 : SchedWrite; // 32-bit divide on RV64I
+def WriteIRem : SchedWrite; // 32-bit or 64-bit remainder
+def WriteIRem32 : SchedWrite; // 32-bit remainder on RV64I
def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
def WriteJmp : SchedWrite; // Jump
@@ -135,6 +137,8 @@ def ReadShiftReg : SchedRead;
def ReadShiftReg32 : SchedRead; // 32-bit shift by register operations on RV64Ix
def ReadIDiv : SchedRead;
def ReadIDiv32 : SchedRead;
+def ReadIRem : SchedRead;
+def ReadIRem32 : SchedRead;
def ReadIMul : SchedRead;
def ReadIMul32 : SchedRead;
def ReadAtomicBA : SchedRead;
``````````
</details>
https://github.com/llvm/llvm-project/pull/84385
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