[llvm] [GlobalISel] Check width of APInts in Reassoc PtrAdd combine (PR #84335)

Thu Mar 7 08:17:02 PST 2024

https://github.com/mbrkusanin updated https://github.com/llvm/llvm-project/pull/84335

>From 16c803af971e74e218d856a1992f966393bcc4e6 Mon Sep 17 00:00:00 2001
From: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
Date: Thu, 7 Mar 2024 16:40:38 +0100
Subject: [PATCH 1/2] [GlobalISel] Check width of APInts in Reassoc PtrAdd
 combine

---
 .../lib/CodeGen/GlobalISel/CombinerHelper.cpp |  3 +-
 .../combine-ptradd-reassociation.mir          | 49 +++++++++++++++++++
 2 files changed, 51 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir

diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 2f18a64ca285bd..d772f3d228d0de 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -4653,7 +4653,8 @@ bool CombinerHelper::matchReassocFoldConstantsInSubTree(GPtrAdd &MI,
     return false;
 
   MatchInfo = [=, &MI](MachineIRBuilder &B) {
-    auto NewCst = B.buildConstant(MRI.getType(Src2Reg), *C1 + *C2);
+    auto NewCst = B.buildConstant(MRI.getType(Src2Reg),
+                                  C1->sextOrTrunc(C2->getBitWidth()) + *C2);
     Observer.changingInstr(MI);
     MI.getOperand(1).setReg(LHSSrc1);
     MI.getOperand(2).setReg(NewCst.getReg(0));
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir
new file mode 100644
index 00000000000000..67c8548f9272a9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir
@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            test_different_sizes_64_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    ; CHECK-LABEL: name: test_different_sizes_64_32
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[INTTOPTR]], [[C]](s32)
+    ; CHECK-NEXT: SI_RETURN implicit [[PTR_ADD]](p1)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_CONSTANT i64 8
+    %2:_(s32) = G_CONSTANT i32 4
+    %3:_(p1) = G_INTTOPTR %0(s64)
+    %4:_(p1) = G_PTR_ADD %3, %1(s64)
+    %5:_(p1) = G_PTR_ADD %4, %2(s32)
+    SI_RETURN implicit %5(p1)
+...
+---
+name:            test_different_sizes_32_64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    ; CHECK-LABEL: name: test_different_sizes_32_64
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[INTTOPTR]], [[C]](s64)
+    ; CHECK-NEXT: SI_RETURN implicit [[PTR_ADD]](p1)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_CONSTANT i64 8
+    %2:_(s32) = G_CONSTANT i32 4
+    %3:_(p1) = G_INTTOPTR %0(s64)
+    %4:_(p1) = G_PTR_ADD %3, %2(s32)
+    %5:_(p1) = G_PTR_ADD %4, %1(s64)
+    SI_RETURN implicit %5(p1)
+...

>From 22faed68b7cf1726d9110e45837afc3e98ad5a01 Mon Sep 17 00:00:00 2001
From: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
Date: Thu, 7 Mar 2024 17:16:30 +0100
Subject: [PATCH 2/2] If constant widths differ pick larger one

---
 llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp           | 9 +++++++--
 .../AMDGPU/GlobalISel/combine-ptradd-reassociation.mir   | 4 ++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index d772f3d228d0de..feb77ff448098f 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -4652,9 +4652,14 @@ bool CombinerHelper::matchReassocFoldConstantsInSubTree(GPtrAdd &MI,
   if (!C2)
     return false;
 
+  // If constant widths differ pick larger one.
+  unsigned BitWidth = std::max(C1->getBitWidth(), C2->getBitWidth());
+  APInt NewConst = C1->sext(BitWidth) + C2->sext(BitWidth);
+  LLT Type =
+      MRI.getType(C1->getBitWidth() > C2->getBitWidth() ? LHSSrc2 : Src2Reg);
+
   MatchInfo = [=, &MI](MachineIRBuilder &B) {
-    auto NewCst = B.buildConstant(MRI.getType(Src2Reg),
-                                  C1->sextOrTrunc(C2->getBitWidth()) + *C2);
+    auto NewCst = B.buildConstant(Type, NewConst);
     Observer.changingInstr(MI);
     MI.getOperand(1).setReg(LHSSrc1);
     MI.getOperand(2).setReg(NewCst.getReg(0));
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir
index 67c8548f9272a9..7920f65eedebb7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir
@@ -13,8 +13,8 @@ body:             |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
     ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY]](s64)
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
-    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[INTTOPTR]], [[C]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[INTTOPTR]], [[C]](s64)
     ; CHECK-NEXT: SI_RETURN implicit [[PTR_ADD]](p1)
     %0:_(s64) = COPY $sgpr0_sgpr1
     %1:_(s64) = G_CONSTANT i64 8

