[llvm] [GISEL][RISCV] IRTranslator for scalable vector load (PR #80006)

[Matt Arsenault via llvm-commits]

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@@ -1198,7 +1198,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
         if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
           report("Generic extload must have a narrower memory type", MI);
       } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
-        if (MMO.getSize() > ValTy.getSizeInBytes())
+        if (TypeSize::isKnownGT(MMO.getType().getSizeInBytes(),
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arsenm wrote:

Verifier test for this would be good 

https://github.com/llvm/llvm-project/pull/80006