[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Sergei Barannikov via llvm-commits]

================
@@ -10984,6 +11087,12 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
     if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP))
       return Match_RequiresV8;
     break;
+  case ARM::tMUL:
+    // The second source operand must be the same register as the destination
+    // operand.
+    if (Inst.getOperand(0).getReg() != Inst.getOperand(3).getReg())
+      return Match_RequiresDestinationRegisterMatchASourceRegister;
----------------
s-barannikov wrote:

It appears the code that checks the constraints is not emitted when ReportMultipleNearMisses is true:
```C++
  if (!ReportMultipleNearMisses)
    emitAsmTiedOperandConstraints(Target, Info, OS, HasOptionalOperands);
```
There is a comment elsewhere:
```
      // FIXME: The tied operands checking is not yet integrated with the
      // framework for reporting multiple near misses.
```
In any case, it seems that if an instruction has a custom converter, the built-in tied operands checking is not performed. 

PS
There is `Match_InvalidTiedOperand` that would be used if tied operand checking was emitted.


https://github.com/llvm/llvm-project/pull/83436