[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Alfie Richards via llvm-commits]

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@@ -10984,6 +11087,12 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
     if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP))
       return Match_RequiresV8;
     break;
+  case ARM::tMUL:
+    // The second source operand must be the same register as the destination
+    // operand.
+    if (Inst.getOperand(0).getReg() != Inst.getOperand(3).getReg())
+      return Match_RequiresDestinationRegisterMatchASourceRegister;
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AlfieRichardsArm wrote:

Hmm yeah I can't see where in `build/lib/Target/ARM/ARMGenAsmMatcher.inc` such operand restrictions would be checked. Is this supported for instruction selection at all do you know? 

https://github.com/llvm/llvm-project/pull/83436