[llvm] [AMDGPU] Rename getNumVGPRBlocks. NFC (PR #84161)
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 7 01:26:02 PST 2024
https://github.com/rovka updated https://github.com/llvm/llvm-project/pull/84161
>From fdf5d5059254b2e2e75ba3fef82b61868d8149df Mon Sep 17 00:00:00 2001
From: Diana Picus <Diana-Magda.Picus at amd.com>
Date: Wed, 6 Mar 2024 11:00:55 +0100
Subject: [PATCH 1/2] [AMDGPU] Rename getNumVGPRBlocks. NGC
Rename getNumVGPRBlocks to getEncodedNumVGPRBlocks, to clarify that
it's using the encoding granule. This is used to program the hardware.
In practice, the hardware will use the alloc granule instead, so this
patch also adds a new helper, getAllocatedNumVGPRBlocks, which can be
useful when driving heuristics.
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 4 ++--
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 ++--
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 21 +++++++++++++------
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 15 +++++++++----
4 files changed, 30 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 37a36b26b947c6..d9970a200804ae 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -868,8 +868,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
&STM, ProgInfo.NumSGPRsForWavesPerEU);
- ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
- &STM, ProgInfo.NumVGPRsForWavesPerEU);
+ ProgInfo.VGPRBlocks =
+ IsaInfo::getEncodedNumVGPRBlocks(&STM, ProgInfo.NumVGPRsForWavesPerEU);
const SIModeRegisterDefaults Mode = MFI->getMode();
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 10999d846e3bb2..b42c1acbd305c3 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5376,8 +5376,8 @@ bool AMDGPUAsmParser::calculateGPRBlocks(
NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
}
- VGPRBlocks =
- IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);
+ VGPRBlocks = IsaInfo::getEncodedNumVGPRBlocks(&getSTI(), NumVGPRs,
+ EnableWavefrontSize32);
SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);
return false;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 63285c06edaf2c..f0dc01644b85da 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1158,14 +1158,23 @@ unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
return std::min(MaxNumVGPRs, AddressableNumVGPRs);
}
-unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
- std::optional<bool> EnableWavefrontSize32) {
- NumVGPRs = alignTo(std::max(1u, NumVGPRs),
- getVGPREncodingGranule(STI, EnableWavefrontSize32));
- // VGPRBlocks is actual number of VGPR blocks minus 1.
- return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;
+static unsigned getNumBlocks(unsigned NumVGPRs, unsigned Granule) {
+ return divideCeil(std::max(1u, NumVGPRs), Granule);
}
+unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
+ std::optional<bool> EnableWavefrontSize32) {
+ return getNumBlocks(NumVGPRs,
+ getVGPREncodingGranule(STI, EnableWavefrontSize32)) -
+ 1;
+}
+
+unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI,
+ unsigned NumVGPRs,
+ std::optional<bool> EnableWavefrontSize32) {
+ return getNumBlocks(NumVGPRs,
+ getVGPRAllocGranule(STI, EnableWavefrontSize32));
+}
} // end namespace IsaInfo
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 9fcb4caca30b01..d827ef3827e2a0 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -316,13 +316,20 @@ unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,
unsigned NumVGPRs);
/// \returns Number of VGPR blocks needed for given subtarget \p STI when
-/// \p NumVGPRs are used.
+/// \p NumVGPRs are used. We actually return the number of blocks -1, since
+/// that's what we encode.
///
/// For subtargets which support it, \p EnableWavefrontSize32 should match the
/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
-unsigned
-getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
- std::optional<bool> EnableWavefrontSize32 = std::nullopt);
+unsigned getEncodedNumVGPRBlocks(
+ const MCSubtargetInfo *STI, unsigned NumVGPRs,
+ std::optional<bool> EnableWavefrontSize32 = std::nullopt);
+
+/// \returns Number of VGPR blocks that need to be allocated for the given
+/// subtarget \p STI when \p NumVGPRs are used.
+unsigned getAllocatedNumVGPRBlocks(
+ const MCSubtargetInfo *STI, unsigned NumVGPRs,
+ std::optional<bool> EnableWavefrontSize32 = std::nullopt);
} // end namespace IsaInfo
>From d915d30c34eb97c2e81b0bf548daea0a444f2fcb Mon Sep 17 00:00:00 2001
From: Diana Picus <Diana-Magda.Picus at amd.com>
Date: Wed, 6 Mar 2024 11:00:55 +0100
Subject: [PATCH 2/2] Rename getNumBlocks and use it in getNumSGPRBlocks
---
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 21 ++++++++++---------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index f0dc01644b85da..2724177b5e8215 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1060,10 +1060,15 @@ unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
}
+static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs,
+ unsigned Granule) {
+ return divideCeil(std::max(1u, NumRegs), Granule);
+}
+
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
- NumSGPRs = alignTo(std::max(1u, NumSGPRs), getSGPREncodingGranule(STI));
// SGPRBlocks is actual number of SGPR blocks minus 1.
- return NumSGPRs / getSGPREncodingGranule(STI) - 1;
+ return getGranulatedNumRegisterBlocks(NumSGPRs, getSGPREncodingGranule(STI)) -
+ 1;
}
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
@@ -1158,22 +1163,18 @@ unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
return std::min(MaxNumVGPRs, AddressableNumVGPRs);
}
-static unsigned getNumBlocks(unsigned NumVGPRs, unsigned Granule) {
- return divideCeil(std::max(1u, NumVGPRs), Granule);
-}
-
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
std::optional<bool> EnableWavefrontSize32) {
- return getNumBlocks(NumVGPRs,
- getVGPREncodingGranule(STI, EnableWavefrontSize32)) -
+ return getGranulatedNumRegisterBlocks(
+ NumVGPRs, getVGPREncodingGranule(STI, EnableWavefrontSize32)) -
1;
}
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI,
unsigned NumVGPRs,
std::optional<bool> EnableWavefrontSize32) {
- return getNumBlocks(NumVGPRs,
- getVGPRAllocGranule(STI, EnableWavefrontSize32));
+ return getGranulatedNumRegisterBlocks(
+ NumVGPRs, getVGPRAllocGranule(STI, EnableWavefrontSize32));
}
} // end namespace IsaInfo
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