[llvm] [RISCV] Insert a freeze before converting select to AND/OR. (PR #84232)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 6 23:10:13 PST 2024
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@@ -481,12 +481,10 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
-; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: addiw a0, a0, 1
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wangpc-pp wrote:
It seems to be a happy surprise? we removed a zero extend here.
https://github.com/llvm/llvm-project/pull/84232
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