[llvm] 68d07bf - [RISCV][NFC] Add helpers for RVV register classes

[via llvm-commits]

Author: Wang Pengcheng
Date: 2024-03-07T14:18:37+08:00
New Revision: 68d07bf34f6b044193c429d9f8cf07500a4775ea

URL: https://github.com/llvm/llvm-project/commit/68d07bf34f6b044193c429d9f8cf07500a4775ea
DIFF: https://github.com/llvm/llvm-project/commit/68d07bf34f6b044193c429d9f8cf07500a4775ea.diff

LOG: [RISCV][NFC] Add helpers for RVV register classes

There are two places in tree that use these helpers and there will
be more future usages.

Reviewers: asb, BeMg, lukel97

Reviewed By: BeMg, lukel97

Pull Request: https://github.com/llvm/llvm-project/pull/84144

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index e46fe8ecb900fc..943c4f2627cf2f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -112,11 +112,33 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
 
   bool doesRegClassHavePseudoInitUndef(
       const TargetRegisterClass *RC) const override {
+    return isVRRegClass(RC);
+  }
+
+  static bool isVRRegClass(const TargetRegisterClass *RC) {
     return RISCV::VRRegClass.hasSubClassEq(RC) ||
            RISCV::VRM2RegClass.hasSubClassEq(RC) ||
            RISCV::VRM4RegClass.hasSubClassEq(RC) ||
            RISCV::VRM8RegClass.hasSubClassEq(RC);
   }
+
+  static bool isVRNRegClass(const TargetRegisterClass *RC) {
+    return RISCV::VRN2M1RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN2M2RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN2M4RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN3M1RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN3M2RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN4M1RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN4M2RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN5M1RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN6M1RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN7M1RegClass.hasSubClassEq(RC) ||
+           RISCV::VRN8M1RegClass.hasSubClassEq(RC);
+  }
+
+  static bool isRVVRegClass(const TargetRegisterClass *RC) {
+    return isVRRegClass(RC) || isVRNRegClass(RC);
+  }
 };
 }
 

diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 6fe0abaccb9d98..ae1a6f179a49e3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -278,21 +278,7 @@ class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
 
 static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
                                const TargetRegisterClass &RC) {
-  return RISCV::VRRegClass.hasSubClassEq(&RC) ||
-         RISCV::VRM2RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRM4RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRM8RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN2M1RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN2M2RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN2M4RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN3M1RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN3M2RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN4M1RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN4M2RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN5M1RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN6M1RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN7M1RegClass.hasSubClassEq(&RC) ||
-         RISCV::VRN8M1RegClass.hasSubClassEq(&RC);
+  return RISCVRegisterInfo::isRVVRegClass(&RC);
 }
 
 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }