[llvm] [RISCV] Insert a freeze before converting select to AND/OR. (PR #84232)

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git-clang-format --diff 0bd9255f8ad9f321dd606365e2bc28447a9976cb fc7fcdb147f10f30414a2b757d4e3e663db9599b -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1efb6ff409..b22eb65f3b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7290,14 +7290,14 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
     // (select x, x, y) -> x | y
     // (select !x, x, y) -> x & y
     if (std::optional<bool> MatchResult = matchSetCC(LHS, RHS, CC, TrueV)) {
-      return DAG.getNode(*MatchResult ? ISD::OR : ISD::AND, DL, VT, DAG.getFreeze(TrueV),
-                         DAG.getFreeze(FalseV));
+      return DAG.getNode(*MatchResult ? ISD::OR : ISD::AND, DL, VT,
+                         DAG.getFreeze(TrueV), DAG.getFreeze(FalseV));
     }
     // (select x, y, x) -> x & y
     // (select !x, y, x) -> x | y
     if (std::optional<bool> MatchResult = matchSetCC(LHS, RHS, CC, FalseV)) {
-      return DAG.getNode(*MatchResult ? ISD::AND : ISD::OR, DL, VT, DAG.getFreeze(TrueV),
-                         DAG.getFreeze(FalseV));
+      return DAG.getNode(*MatchResult ? ISD::AND : ISD::OR, DL, VT,
+                         DAG.getFreeze(TrueV), DAG.getFreeze(FalseV));
     }
   }
 

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https://github.com/llvm/llvm-project/pull/84232