[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Sergei Barannikov via llvm-commits]

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@@ -12811,11 +12930,24 @@ unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
     if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
       return Match_Success;
     return Match_rGPR;
-  case MCK_GPRPair:
-    if (Op.isReg() &&
-        MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
+  // If trying to match a VecListDPair with a Q register, convert Q to list
+  case MCK_VecListDPair:
+    if (Op.isQReg() && !hasMVE()) {
+      auto DPair = getDRegFromQReg(Op.getReg());
+      DPair = MRI->getMatchingSuperReg(
+          DPair, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
+      Op.setVecListDPair(DPair);
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s-barannikov wrote:

This method shouldn't mutate the operand.
You may want to modify the `ARMOperand::isVecListDPair` instead to accept single register and `ARMOPerand::addXXXOperand` to render the register as a list.


https://github.com/llvm/llvm-project/pull/83436