[llvm] [AArch64][MachinePipeliner] Add pipeliner support for AArch64 (PR #79589)

[Yuta Mukai via llvm-commits]

ytmukai wrote:

> why set pipeliner-enable-copytophi flag to 0

pipeliner-enable-copytophi often makes DDG unschedulable.
The following is an example. The debug message indicates that the schedule failed.
https://godbolt.org/z/66avx9vvh
(The original C source is https://godbolt.org/z/Ksb3o45Yv)

In this case, SU#4(`SU(4):   %35:gpr64 = nuw ADDXrr %2:gpr64common`) is forced to schedule after the nodes that refer `%2` (such as `SU(3):   ST1D %33:zpr, %31:ppr_3b, %14:gpr64common, %2:gpr64common`) so that `%2` and `%35` do not live at the same time by pipeliner-enable-copytophi.
However, SU#4 has a real successor SU#6(`SU(6):   dead $xzr = SUBSXrr %29:gpr64, %35:gpr64`), and it is always placed in stage#0 because it is part of the loop control.
As a result, scheduling becomes almost impossible.

I think pipeliner-enable-copytophi needs to be disabled according to the architecture.

> In some cases, this can lead to a compilation failure because the compiler may use registers before register definitions.

I have never seen such a case. What are the conditions of this failure?

https://github.com/llvm/llvm-project/pull/79589