[llvm] [RISCV][NFC] Add helpers for RVV register classes (PR #84144)
via llvm-commits
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Wed Mar 6 01:10:50 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Wang Pengcheng (wangpc-pp)
<details>
<summary>Changes</summary>
There are two places in tree that use these helpers and there will
be more future usages.
---
Full diff: https://github.com/llvm/llvm-project/pull/84144.diff
2 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.h (+20-2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+3-15)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index e46fe8ecb900fc..f5b4cac7dffd74 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -110,13 +110,31 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
return RC;
}
- bool doesRegClassHavePseudoInitUndef(
- const TargetRegisterClass *RC) const override {
+ bool isRVVRegClass(const TargetRegisterClass *RC) const {
return RISCV::VRRegClass.hasSubClassEq(RC) ||
RISCV::VRM2RegClass.hasSubClassEq(RC) ||
RISCV::VRM4RegClass.hasSubClassEq(RC) ||
RISCV::VRM8RegClass.hasSubClassEq(RC);
}
+
+ bool isRVVSegmentRegClass(const TargetRegisterClass *RC) const {
+ return RISCV::VRN2M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN2M2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN2M4RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN3M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN3M2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN4M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN4M2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN5M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN6M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN7M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN8M1RegClass.hasSubClassEq(RC);
+ }
+
+ bool doesRegClassHavePseudoInitUndef(
+ const TargetRegisterClass *RC) const override {
+ return isRVVRegClass(RC);
+ }
};
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 6fe0abaccb9d98..e499f77fb7772b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -14,6 +14,7 @@
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
+#include "RISCVRegisterInfo.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
@@ -278,21 +279,8 @@ class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
const TargetRegisterClass &RC) {
- return RISCV::VRRegClass.hasSubClassEq(&RC) ||
- RISCV::VRM2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRM4RegClass.hasSubClassEq(&RC) ||
- RISCV::VRM8RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN2M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN2M2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN2M4RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN3M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN3M2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN4M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN4M2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN5M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN6M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN7M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN8M1RegClass.hasSubClassEq(&RC);
+ auto &RegInfo = static_cast<const RISCVRegisterInfo &>(TRI);
+ return RegInfo.isRVVRegClass(&RC) || RegInfo.isRVVSegmentRegClass(&RC);
}
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
``````````
</details>
https://github.com/llvm/llvm-project/pull/84144
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