[llvm] [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (PR #76644)

Sizov Nikita via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 5 13:36:26 PST 2024

Previous message: [llvm] [RISCV] Always use signed APSInt in getExactInteger. (PR #84070)
Next message: [llvm] [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (PR #76644)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/snikitav edited https://github.com/llvm/llvm-project/pull/76644

Previous message: [llvm] [RISCV] Always use signed APSInt in getExactInteger. (PR #84070)
Next message: [llvm] [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (PR #76644)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list