[llvm] [RISC-V] Fix crash with late stack realignment requirement (PR #83496)

[Nemanja Ivanovic via llvm-commits]

nemanjai wrote:

...
> > I suppose we could solve it very pessimistically for the Global/CPI case by adding a lui/addi pair into the register that gets freed with the first load/store (and addi for the immediate case), but that seems worse than the potential stack re-alignment for the E ABI. Especially since we would presumably have to restore the address if the register isn't dead.
> 
> The Global/CPI case should be independent of the stack align. Those should only come from user loads/stores. I wonder if we should be splitting 64-bit loads/stores during isel instead of generating pseudos.

I'm not sure I fully follow how this will help resolve this problem. Do you mean that we would set the alignment of the paired registers to 4, expand the loads/stores of `f64` to the two loads/stores plus the necessary `build_pair`/split nodes? Then we can ensure that the loads/stores are able to access each of the pieces just as we do with any other load/store and if we end up spilling any pairs, we won't have the re-alignment issue?


https://github.com/llvm/llvm-project/pull/83496