[llvm] [Hexagon] Fix shift value when folding shl DAG node (PR #83853)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 5 01:47:57 PST 2024
https://github.com/yandalur updated https://github.com/llvm/llvm-project/pull/83853
>From 041154397bfd9eb69ec4febda265d2becc2f5e26 Mon Sep 17 00:00:00 2001
From: Yashas Andaluri <yandalur at qti.qualcomm.com>
Date: Tue, 7 Feb 2023 19:21:08 +0530
Subject: [PATCH 1/2] [Hexagon] Fix shift value when folding shl DAG node
When folding (or (shl xx, s), (zext y)) to (COMBINE (shl xx, s-32), y),
fix resulting shift value in HexagonISD::COMBINE node to
not generate negative values.
---
.../Target/Hexagon/HexagonISelLowering.cpp | 2 +-
.../CodeGen/Hexagon/isel-fold-shl-zext.ll | 48 +++++++++++++++++++
2 files changed, 49 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 13691053ddd707..eda1150835a1f4 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3543,7 +3543,7 @@ HexagonTargetLowering::PerformDAGCombine(SDNode *N,
unsigned A = Amt->getZExtValue();
SDValue S = Shl.getOperand(0);
SDValue T0 = DCI.DAG.getNode(ISD::SHL, dl, ty(S), S,
- DCI.DAG.getConstant(32 - A, dl, MVT::i32));
+ DCI.DAG.getConstant(A - 32, dl, MVT::i32));
SDValue T1 = DCI.DAG.getZExtOrTrunc(T0, dl, MVT::i32);
SDValue T2 = DCI.DAG.getZExtOrTrunc(Z, dl, MVT::i32);
return DCI.DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {T1, T2});
diff --git a/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll b/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
new file mode 100644
index 00000000000000..8008e173d050ec
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=hexagon-unknown-elf < %s | FileCheck %s
+
+; In ISelLowering, when folding nodes (or (shl xx, s), (zext y))
+; to (COMBINE (shl xx, s-32), y) where s >= 32,
+; check that resulting shift value does not create an undef
+
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+; Function Attrs: nofree nosync nounwind memory(readwrite, inaccessiblemem: none)
+define dso_local void @foo(i64* nocapture noundef %buf, i32 %a, i32 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: {
+; CHECK-NEXT: r2 = addasl(r2,r1,#1)
+; CHECK-NEXT: r3 = asl(r1,#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r2 = addasl(r2,r1,#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: memd(r0+#8) = r3:2
+; CHECK-NEXT: }
+entry:
+ %arrayidx = getelementptr inbounds i64, i64* %buf, i32 1
+ %add0 = shl nsw i32 %a, 1
+ %add1 = add nsw i32 %add0, %b
+ %add2 = add nsw i32 %add1, %add0
+ %ext0 = zext i32 %add0 to i64
+ %shift0 = shl nuw i64 %ext0, 32
+ %ext1 = zext i32 %add2 to i64
+ %or0 = or i64 %shift0, %ext1
+ store i64 %or0, i64* %arrayidx, align 8, !tbaa !2
+ ret void
+}
+
+attributes #0 = { nofree nosync nounwind memory(readwrite, inaccessiblemem: none) "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv71" "target-features"="+v71,-long-calls" }
+
+!llvm.module.flags = !{!0, !1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
>From 87819d86e60720ab8f7691ea12eeb0e526c3643f Mon Sep 17 00:00:00 2001
From: Yashas Andaluri <quic_yandalur at quicinc.com>
Date: Tue, 5 Mar 2024 15:16:43 +0530
Subject: [PATCH 2/2] Update lit test
---
.../CodeGen/Hexagon/isel-fold-shl-zext.ll | 23 +++++--------------
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll b/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
index 8008e173d050ec..5fa50231005148 100644
--- a/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
+++ b/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=hexagon-unknown-elf < %s | FileCheck %s
; In ISelLowering, when folding nodes (or (shl xx, s), (zext y))
@@ -10,19 +9,19 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i
target triple = "hexagon"
; Function Attrs: nofree nosync nounwind memory(readwrite, inaccessiblemem: none)
-define dso_local void @foo(i64* nocapture noundef %buf, i32 %a, i32 %b) local_unnamed_addr #0 {
+define dso_local void @foo(i64* nocapture noundef %buf, i32 %a, i32 %b) local_unnamed_addr {
; CHECK-LABEL: foo:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: {
-; CHECK-NEXT: r2 = addasl(r2,r1,#1)
-; CHECK-NEXT: r3 = asl(r1,#1)
+; CHECK-NEXT: r[[REG0:[0-9]+]] = addasl(r2,r1,#1)
+; CHECK-NEXT: r[[REG2:[0-9]+]] = asl(r1,#1)
; CHECK-NEXT: }
; CHECK-NEXT: {
-; CHECK-NEXT: r2 = addasl(r2,r1,#1)
+; CHECK-NEXT: r[[REG1:[0-9]+]] = addasl(r[[REG0]],r1,#1)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
-; CHECK-NEXT: memd(r0+#8) = r3:2
+; CHECK-NEXT: memd(r0+#8) = r[[REG2]]:[[REG1]]
; CHECK-NEXT: }
entry:
%arrayidx = getelementptr inbounds i64, i64* %buf, i32 1
@@ -33,16 +32,6 @@ entry:
%shift0 = shl nuw i64 %ext0, 32
%ext1 = zext i32 %add2 to i64
%or0 = or i64 %shift0, %ext1
- store i64 %or0, i64* %arrayidx, align 8, !tbaa !2
+ store i64 %or0, i64* %arrayidx, align 8
ret void
}
-
-attributes #0 = { nofree nosync nounwind memory(readwrite, inaccessiblemem: none) "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv71" "target-features"="+v71,-long-calls" }
-
-!llvm.module.flags = !{!0, !1}
-
-!0 = !{i32 1, !"wchar_size", i32 4}
-!1 = !{i32 7, !"frame-pointer", i32 2}
-!2 = !{!3, !3, i64 0}
-!3 = !{!"omnipotent char", !4, i64 0}
-!4 = !{!"Simple C/C++ TBAA"}
More information about the llvm-commits
mailing list