[llvm] [Hexagon] Fix shift value when folding shl DAG node (PR #83853)

[Ikhlas Ajbar via llvm-commits]

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iajbar wrote:

If allocated registers change, this check will fail. 
; CHECK-NEXT:     r2 = addasl(r2,r1,#1)
; CHECK-NEXT:     r3 = asl(r1,#1)
What about using:  r[[REG1:[0-9]+]] and  r[[REG2:[0-9]+]] instead?

https://github.com/llvm/llvm-project/pull/83853