[llvm] [SelectionDAG] Change computeAliasing signature from optional<uint64> to LocationSize. (PR #83017)

[Luke Lau via llvm-commits]

lukel97 wrote:

Thanks for landing this, this [fixes a miscompile](https://github.com/llvm/llvm-project/commit/63725ab1196ac50509ad382fc12c56f6d8b5d874) we were seeing on RISC-V on SPEC CPU 2017 with a specific vector configuration `-mrvv-vector-bits=zvl`.

Would you have any objections to backporting this to 18.x?

https://github.com/llvm/llvm-project/pull/83017