[llvm] [X86] Improve transform for add-like nodes to `add` (PR #83691)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 3 08:54:43 PST 2024
================
@@ -1560,21 +1560,38 @@ let Predicates = [HasNDD] in {
}
// Depositing value to 8/16 bit subreg:
-def : Pat<(or (and GR64:$dst, -256),
+def : Pat<(or (and GR64:$dst, -256),
(i64 (zextloadi8 addr:$src))),
- (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>;
+ (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>;
-def : Pat<(or (and GR32:$dst, -256),
+def : Pat<(or (and GR32:$dst, -256),
(i32 (zextloadi8 addr:$src))),
- (INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>;
+ (INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>;
-def : Pat<(or (and GR64:$dst, -65536),
+def : Pat<(or (and GR64:$dst, -65536),
(i64 (zextloadi16 addr:$src))),
(INSERT_SUBREG (i64 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>;
-def : Pat<(or (and GR32:$dst, -65536),
+def : Pat<(or (and GR32:$dst, -65536),
(i32 (zextloadi16 addr:$src))),
- (INSERT_SUBREG (i32 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>;
+ (INSERT_SUBREG (i32 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>;
+
+// We convert or -> add when the or is disjoint so need to handle for add as well.
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goldsteinn wrote:
These are `(or (and...), (zextload))`?
https://github.com/llvm/llvm-project/pull/83691
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