[llvm] [X86] Transform `(xor x, SIGN_BIT)` -> `(add x, SIGN_BIT)` 32 bit and smaller scalars (PR #83659)

[Craig Topper via llvm-commits]

================
@@ -52128,7 +52128,19 @@ static SDValue combineXor(SDNode *N, SelectionDAG &DAG,
   if (SDValue R = combineBMILogicOp(N, DAG, Subtarget))
     return R;
 
-  return combineFneg(N, DAG, DCI, Subtarget);
+  if (SDValue R = combineFneg(N, DAG, DCI, Subtarget))
+    return R;
+
+  // (xor x, SIGN_BIT) == (add x, SIGN_BIT), since we can lower `add` with `lea`
+  // which can be fused with shift/eliminate register moves, its preferable.
+  if (VT.isScalarInteger() && VT.getScalarSizeInBits() <= 32) {
----------------
topperc wrote:

Don't we already do this for == 32 in tablegen?

```
def : Pat<(xor GR8:$src1, -128),                                                 
          (ADD8ri GR8:$src1, -128)>;                                             
def : Pat<(xor GR16:$src1, -32768),                                              
          (ADD16ri GR16:$src1, -32768)>;                                         
def : Pat<(xor GR32:$src1, -2147483648),                                         
          (ADD32ri GR32:$src1, -2147483648)>;
```

https://github.com/llvm/llvm-project/pull/83659