[llvm] 8b26e60 - [RISCV] Use the VR register allocation order for VM. (#83664)

[via llvm-commits]

Author: Craig Topper
Date: 2024-03-02T17:06:38-08:00
New Revision: 8b26e609e032b4535b90514e22875bfaa194216c

URL: https://github.com/llvm/llvm-project/commit/8b26e609e032b4535b90514e22875bfaa194216c
DIFF: https://github.com/llvm/llvm-project/commit/8b26e609e032b4535b90514e22875bfaa194216c.diff

LOG: [RISCV] Use the VR register allocation order for VM. (#83664)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 53838d6e540123..225b57554c1dc0 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -585,9 +585,7 @@ def GPRPair : RegisterClass<"RISCV", [XLenPairFVT], 64, (add
 )>;
 
 // The register class is added for inline assembly for vector mask types.
-def VM : VReg<VMaskVTs,
-           (add (sequence "V%u", 8, 31),
-                (sequence "V%u", 0, 7)), 1>;
+def VM : VReg<VMaskVTs, (add VR), 1>;
 
 foreach m = LMULList in {
   foreach nf = NFList<m>.L in {