[llvm] [llvm][arm] add T1 and T2 assembly optoins for vlldm and vlstm (PR #83685)

[via llvm-commits]

github-actions[bot] wrote:

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git-clang-format --diff ca827d53c5524409dcca5ade3949b25f38a60fef 8e953d6f7275603944c7ae220fe7109d0157b2df -- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp llvm/unittests/Target/ARM/MachineInstrTest.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 2f00ed8541..c320bf723c 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6092,7 +6092,7 @@ bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
     bool AllowOutOfBoundReg = Mnemonic == "vlldm" || Mnemonic == "vlstm";
     return parseRegisterList(Operands, !Mnemonic.starts_with("clr"), false,
                              AllowOutOfBoundReg);
-}
+  }
   case AsmToken::Dollar:
   case AsmToken::Hash: {
     // #42 -> immediate
@@ -7602,7 +7602,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
 
   const unsigned Opcode = Inst.getOpcode();
   switch (Opcode) {
-case ARM::VLLDM:
+  case ARM::VLLDM:
   case ARM::VLLDM_T2:
   case ARM::VLSTM:
   case ARM::VLSTM_T2: {
@@ -8764,7 +8764,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
   }
 
   switch (Inst.getOpcode()) {
-case ARM::VLLDM:
+  case ARM::VLLDM:
   case ARM::VLSTM: {
     // In some cases both T1 and T2 are valid, causing tablegen pick T1 instead
     // of T2

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https://github.com/llvm/llvm-project/pull/83685