[llvm] [X86][CodeGen] Support long instruction fixup for APX NDD instructions (PR #83578)
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 2 04:54:30 PST 2024
================
@@ -613,6 +613,89 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::CALL64m_RVMARKER:
expandCALL_RVMARKER(MBB, MBBI);
return true;
+ case X86::ADD32mi_ND:
+ case X86::ADD64mi32_ND:
+ case X86::SUB32mi_ND:
+ case X86::SUB64mi32_ND:
+ case X86::AND32mi_ND:
+ case X86::AND64mi32_ND:
+ case X86::OR32mi_ND:
+ case X86::OR64mi32_ND:
+ case X86::XOR32mi_ND:
+ case X86::XOR64mi32_ND:
+ case X86::ADC32mi_ND:
+ case X86::ADC64mi32_ND:
+ case X86::SBB32mi_ND:
+ case X86::SBB64mi32_ND: {
+ // It's possible for an EVEX-encoded legacy instruction to reach the 15-byte
+ // instruction length limit: 4 bytes of EVEX prefix + 1 byte of opcode + 1
+ // byte of ModRM + 1 byte of SIB + 4 bytes of displacement + 4 bytes of
+ // immediate = 15 bytes in total, e.g.
+ //
+ // subq $184, %fs:257(%rbx, %rcx), %rax
+ //
+ // In such a case, no additional (ADSIZE or segment override) prefix can be
+ // used. To resolve the issue, we split the “long” instruction into 2
+ // instructions:
+ //
+ // movq %fs:257(%rbx, %rcx),%rax
+ // subq $184, %rax
+ const MachineOperand &ImmOp =
+ MI.getOperand(MI.getNumExplicitOperands() - 1);
+ // If the immediate is a expr, conservatively estimate 4 bytes.
+ if (ImmOp.isImm() && isInt<8>(ImmOp.getImm()))
+ return false;
+ int MemOpNo = X86::getFirstAddrOperandIdx(MI);
+ const MachineOperand &DispOp = MI.getOperand(MemOpNo + X86::AddrDisp);
+ // If the displacement is a expr, conservatively estimate 4 bytes.
+ if (DispOp.isImm() && isInt<8>(DispOp.getImm()))
+ return false;
+ // There can only be one of three: SIB, segment override register, ADSIZE
+ Register Segment = MI.getOperand(MemOpNo + X86::AddrSegmentReg).getReg();
----------------
phoebewang wrote:
unsigned Count = !!MI.getOperand(MemOpNo + X86::AddrSegmentReg).getReg();
https://github.com/llvm/llvm-project/pull/83578
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