[llvm] [RISCV] Use the VR allocation order for VM. (PR #83664)
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Fri Mar 1 23:58:10 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/83664.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.td (+1-3)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 53838d6e540123..225b57554c1dc0 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -585,9 +585,7 @@ def GPRPair : RegisterClass<"RISCV", [XLenPairFVT], 64, (add
)>;
// The register class is added for inline assembly for vector mask types.
-def VM : VReg<VMaskVTs,
- (add (sequence "V%u", 8, 31),
- (sequence "V%u", 0, 7)), 1>;
+def VM : VReg<VMaskVTs, (add VR), 1>;
foreach m = LMULList in {
foreach nf = NFList<m>.L in {
``````````
</details>
https://github.com/llvm/llvm-project/pull/83664
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