[llvm] [RISC-V] Fix crash with late stack realignment requirement (PR #83496)

[Craig Topper via llvm-commits]

topperc wrote:

> > > Another possible solution would be to change the alignment requirement for `GPRPair` to 32. Perhaps this would need to only be done when the E extension is enabled, so maybe it would require a separate register class. In any case, thought I'd propose these suggestions and we can converge on some solution to this problem.
> > 
> > 
> > It should have an alignment of 32, but then we have potential issue spilling a GPRPair. We need to be able to calculate the address of the second half of the spill slot without needing a temporary register. By having the entire spill slot aligned to 8, we guarantee that we can fold +4 into the load/store address in `RISCVExpandPseudo::expandRV32ZdinxStore` and `RISCVExpandPseudo::expandRV32ZdinxLoad`. Maybe there's a better way to solve that?
> 
> I suppose we could solve it very pessimistically for the Global/CPI case by adding a lui/addi pair into the register that gets freed with the first load/store (and addi for the immediate case), but that seems worse than the potential stack re-alignment for the E ABI. Especially since we would presumably have to restore the address if the register isn't dead.

The Global/CPI case should be independent of the stack align. Those should only come from user loads/stores. I wonder if we should be splitting 64-bit loads/stores during isel instead of generating pseudos.

https://github.com/llvm/llvm-project/pull/83496