[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Alfie Richards via llvm-commits]

================
@@ -1474,7 +1513,7 @@ void AsmMatcherInfo::buildOperandMatchInfo() {
         OperandMask |= maskTrailingOnes<unsigned>(NumOptionalOps + 1)
                        << (i - NumOptionalOps);
       }
-      if (Op.Class->IsOptional)
+      if (Op.Class->IsOptional && Op.Class->OptionalShouldOffsetCustomParsers)
----------------
AlfieRichardsArm wrote:

Heres a little more context for the example: 
Snippet of tableget for VMOVv4f32:
```
def VMOVv4f32 { // InstructionEncoding Instruction InstTemplate Encoding InstARM NeonI NDataI N1ModImm
  field bits<32> Inst = { 1, 1, 1, 1, 0, 0, 1, SIMM{7}, 1, Vd{4}, 0, 0, 0, SIMM{6}, SIMM{5}, SIMM{4}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 1, 1, 1, 0, 1, 0, 1, SIMM{3}, SIMM{2}, SIMM{1}, SIMM{0} };
  field bits<32> Unpredictable = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  int Size = 4;
  string DecoderNamespace = "NEONData";
  list<Predicate> Predicates = [HasNEON];
  string DecoderMethod = "DecodeVMOVModImmInstruction";
  bit hasCompleteDecoder = 1;
  string Namespace = "ARM";
  dag OutOperandList = (outs QPR:$Vd);
  dag InOperandList = (ins nImmVMOVF32:$SIMM, pred:$p);
  string AsmString = "vmov${p}.f32  $Vd, $SIMM";
  ...
  ```
With an input like:
```
vmoveq.f32 q2, #0.1
```

In this case before this change the parser for `nImmVMOVF32` (which has parser class `FPImmOperand`) was being applied to `Vd` because `${p}` was present in this case and the parser was assuming that it would not be present (the default behaviour previously). 

This flag and always adding _something_ to the OperandVector was the solution to this. 

Also see `Target.td:957` where I try describe this a bit also.

https://github.com/llvm/llvm-project/pull/83436