[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Alfie Richards via llvm-commits]

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@@ -1724,6 +1733,11 @@ class Target {
   // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
   // for all opcodes if this flag is set to 0.
   int AllowRegisterRenaming = 0;
+
+  // SortBySize = Should the assembly matcher prefer the smaller
+  // instructions. 1 if the instruction set should sort by size,
+  // 0 otherwise.
+  int SortBySize = 0;
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AlfieRichardsArm wrote:

This has been pulled out to https://github.com/llvm/llvm-project/pull/83587

https://github.com/llvm/llvm-project/pull/83436