[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Alfie Richards via llvm-commits]

================
@@ -1724,6 +1733,11 @@ class Target {
   // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
   // for all opcodes if this flag is set to 0.
   int AllowRegisterRenaming = 0;
+
+  // SortBySize = Should the assembly matcher prefer the smaller
+  // instructions. 1 if the instruction set should sort by size,
+  // 0 otherwise.
+  int SortBySize = 0;
----------------
AlfieRichardsArm wrote:

Just to clarify you would like the SortBySize target option (renamed as requested) and machinery to be in a separate patch? 
I am happy to do this, however the ARM target doesn't work with this turned on without the rest of the patch, so the patch to add this option would not turn it on for the ARM target?

https://github.com/llvm/llvm-project/pull/83436