[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Ivan Kosarev via llvm-commits]

================
@@ -1724,6 +1733,11 @@ class Target {
   // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
   // for all opcodes if this flag is set to 0.
   int AllowRegisterRenaming = 0;
+
+  // SortBySize = Should the assembly matcher prefer the smaller
+  // instructions. 1 if the instruction set should sort by size,
+  // 0 otherwise.
+  int SortBySize = 0;
----------------
kosarev wrote:

Please address this with a separate patch.

The `Sort` bit in the name sounds like a reference to an implementation detail. Can we just directly say the implied and name it something like `PreferSmallerInstructions`?

The type should be `bit`, not `int`?

https://github.com/llvm/llvm-project/pull/83436