[llvm] [SystemZ] Enable MachineCombiner for FP reassociation (PR #83546)
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Fri Mar 1 01:29:46 PST 2024
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git-clang-format --diff d41615e91a108bd1ae41361be97c569691ab9ebb fab2c858e18e1239201f579c223b54a1debfd7d6 -- llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp llvm/include/llvm/CodeGen/MachineCombinerPattern.h llvm/include/llvm/CodeGen/TargetInstrInfo.h llvm/lib/CodeGen/MachineCombiner.cpp llvm/lib/Target/SystemZ/SystemZ.h llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.h llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86InstrInfo.h
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diff --git a/llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp b/llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp
index d441b8bbc8..670743720f 100644
--- a/llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp
@@ -42,15 +42,15 @@ class SystemZFinalizeReassociation : public MachineFunctionPass {
public:
static char ID;
SystemZFinalizeReassociation()
- : MachineFunctionPass(ID), TII(nullptr), MRI(nullptr) {
- initializeSystemZFinalizeReassociationPass(*PassRegistry::getPassRegistry());
+ : MachineFunctionPass(ID), TII(nullptr), MRI(nullptr) {
+ initializeSystemZFinalizeReassociationPass(
+ *PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override;
private:
-
bool visitMBB(MachineBasicBlock &MBB);
const SystemZInstrInfo *TII;
@@ -64,8 +64,8 @@ char SystemZFinalizeReassociation::ID = 0;
INITIALIZE_PASS(SystemZFinalizeReassociation, "systemz-finalize-reassoc",
"SystemZ Finalize Reassociation", false, false)
-FunctionPass *llvm::
-createSystemZFinalizeReassociationPass(SystemZTargetMachine &TM) {
+FunctionPass *
+llvm::createSystemZFinalizeReassociationPass(SystemZTargetMachine &TM) {
return new SystemZFinalizeReassociation();
}
@@ -79,15 +79,15 @@ bool SystemZFinalizeReassociation::visitMBB(MachineBasicBlock &MBB) {
for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
unsigned PseudoOpcode = MI.getOpcode();
unsigned TargetOpcode =
- PseudoOpcode == SystemZ::WFADB_CCPseudo ? SystemZ::WFADB
- : PseudoOpcode == SystemZ::WFASB_CCPseudo ? SystemZ::WFASB
- : PseudoOpcode == SystemZ::WFSDB_CCPseudo ? SystemZ::WFSDB
- : PseudoOpcode == SystemZ::WFSSB_CCPseudo ? SystemZ::WFSSB
- : PseudoOpcode == SystemZ::WFMDB_CCPseudo ? SystemZ::WFMDB
- : PseudoOpcode == SystemZ::WFMSB_CCPseudo ? SystemZ::WFMSB
- : PseudoOpcode == SystemZ::WFMADB_CCPseudo ? SystemZ::WFMADB
- : PseudoOpcode == SystemZ::WFMASB_CCPseudo ? SystemZ::WFMASB
- : 0;
+ PseudoOpcode == SystemZ::WFADB_CCPseudo ? SystemZ::WFADB
+ : PseudoOpcode == SystemZ::WFASB_CCPseudo ? SystemZ::WFASB
+ : PseudoOpcode == SystemZ::WFSDB_CCPseudo ? SystemZ::WFSDB
+ : PseudoOpcode == SystemZ::WFSSB_CCPseudo ? SystemZ::WFSSB
+ : PseudoOpcode == SystemZ::WFMDB_CCPseudo ? SystemZ::WFMDB
+ : PseudoOpcode == SystemZ::WFMSB_CCPseudo ? SystemZ::WFMSB
+ : PseudoOpcode == SystemZ::WFMADB_CCPseudo ? SystemZ::WFMADB
+ : PseudoOpcode == SystemZ::WFMASB_CCPseudo ? SystemZ::WFMASB
+ : 0;
if (TargetOpcode) {
// PeepholeOptimizer will not fold any loads across basic blocks, which
// however seems beneficial, so do it here:
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 652980d3c2..9a1150df03 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -350,8 +350,7 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
// Return true if the flags of N and the subtarget allows for reassociation.
bool isReassociable(SDNode *N) const {
return N->getFlags().hasAllowReassociation() &&
- N->getFlags().hasNoSignedZeros() &&
- Subtarget->hasVector();
+ N->getFlags().hasNoSignedZeros() && Subtarget->hasVector();
}
public:
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 1d8db507e3..487f1d56a6 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -674,7 +674,7 @@ MachineInstr *SystemZInstrInfo::optimizeLoadInstr(MachineInstr &MI,
MachineOperand LHS = MI.getOperand(1);
MachineOperand RHS = MI.getOperand(2);
bool IsTernary =
- (RegMemOpcode == SystemZ::MADB || RegMemOpcode == SystemZ::MAEB);
+ (RegMemOpcode == SystemZ::MADB || RegMemOpcode == SystemZ::MAEB);
MachineOperand *AccMO = IsTernary ? &MI.getOperand(3) : nullptr;
if ((RegMemOpcode == SystemZ::SDB || RegMemOpcode == SystemZ::SEB) &&
FoldAsLoadDefReg != RHS.getReg())
@@ -688,7 +688,8 @@ MachineInstr *SystemZInstrInfo::optimizeLoadInstr(MachineInstr &MI,
DefMI->getParent() != MI.getParent()) {
unsigned NumUsers = 0;
for (MachineInstr &UI : MRI->use_nodbg_instructions(RegMO.getReg())) {
- NumUsers++; (void)UI;
+ NumUsers++;
+ (void)UI;
}
if (NumUsers > MaxUsersGlobalFold)
return nullptr;
@@ -697,12 +698,12 @@ MachineInstr *SystemZInstrInfo::optimizeLoadInstr(MachineInstr &MI,
MachineOperand &Base = DefMI->getOperand(1);
MachineOperand &Disp = DefMI->getOperand(2);
MachineOperand &Indx = DefMI->getOperand(3);
- if (Base.isReg()) // Could be a FrameIndex.
+ if (Base.isReg()) // Could be a FrameIndex.
Base.setIsKill(false);
Indx.setIsKill(false);
MachineInstrBuilder MIB =
- BuildMI(*MI.getParent(), MI, DL, get(RegMemOpcode), DstReg);
+ BuildMI(*MI.getParent(), MI, DL, get(RegMemOpcode), DstReg);
if (IsTernary)
MIB.add(*AccMO);
MIB.add(RegMO);
@@ -1126,7 +1127,7 @@ bool SystemZInstrInfo::IsReassociableAdd(const MachineInstr *MI) const {
case SystemZ::WFADB_CCPseudo:
case SystemZ::WFASB_CCPseudo:
return hasReassocFlags(MI) &&
- MI->findRegisterDefOperandIdx(SystemZ::CC, true/*isDead*/) != -1;
+ MI->findRegisterDefOperandIdx(SystemZ::CC, true /*isDead*/) != -1;
default:
break;
}
@@ -1154,7 +1155,8 @@ bool SystemZInstrInfo::getFMAPatterns(
for (const auto &MO : Instr.explicit_operands())
if (!(MO.isReg() && MO.getReg().isVirtual() && !MO.getSubReg()))
return false;
- const TargetRegisterClass *DefRC = MRI->getRegClass(Instr.getOperand(0).getReg());
+ const TargetRegisterClass *DefRC =
+ MRI->getRegClass(Instr.getOperand(0).getReg());
if (!DefRC->hasSubClassEq(RC) && !DefRC->hasSuperClassEq(RC))
return false;
return true;
@@ -1227,7 +1229,7 @@ void SystemZInstrInfo::finalizeInsInstrs(
MachineInstr &Root, MachineCombinerPattern &P,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {
const TargetRegisterInfo *TRI =
- Root.getParent()->getParent()->getSubtarget().getRegisterInfo();
+ Root.getParent()->getParent()->getSubtarget().getRegisterInfo();
for (auto *Inst : InsInstrs) {
switch (Inst->getOpcode()) {
case SystemZ::WFADB_CCPseudo:
@@ -1240,7 +1242,8 @@ void SystemZInstrInfo::finalizeInsInstrs(
case SystemZ::WFMASB_CCPseudo:
Inst->addRegisterDead(SystemZ::CC, TRI);
break;
- default: break;
+ default:
+ break;
}
}
}
@@ -1279,17 +1282,28 @@ std::optional<unsigned>
SystemZInstrInfo::getInverseOpcode(unsigned Opcode) const {
// fadd <=> fsub in various forms.
switch (Opcode) {
- case SystemZ::VFADB: return SystemZ::VFSDB;
- case SystemZ::VFASB: return SystemZ::VFSSB;
- case SystemZ::WFAXB: return SystemZ::WFSXB;
- case SystemZ::WFADB_CCPseudo: return SystemZ::WFSDB_CCPseudo;
- case SystemZ::WFASB_CCPseudo: return SystemZ::WFSSB_CCPseudo;
- case SystemZ::VFSDB: return SystemZ::VFADB;
- case SystemZ::VFSSB: return SystemZ::VFASB;
- case SystemZ::WFSXB: return SystemZ::WFAXB;
- case SystemZ::WFSDB_CCPseudo: return SystemZ::WFADB_CCPseudo;
- case SystemZ::WFSSB_CCPseudo: return SystemZ::WFASB_CCPseudo;
- default: return std::nullopt;
+ case SystemZ::VFADB:
+ return SystemZ::VFSDB;
+ case SystemZ::VFASB:
+ return SystemZ::VFSSB;
+ case SystemZ::WFAXB:
+ return SystemZ::WFSXB;
+ case SystemZ::WFADB_CCPseudo:
+ return SystemZ::WFSDB_CCPseudo;
+ case SystemZ::WFASB_CCPseudo:
+ return SystemZ::WFSSB_CCPseudo;
+ case SystemZ::VFSDB:
+ return SystemZ::VFADB;
+ case SystemZ::VFSSB:
+ return SystemZ::VFASB;
+ case SystemZ::WFSXB:
+ return SystemZ::WFAXB;
+ case SystemZ::WFSDB_CCPseudo:
+ return SystemZ::WFADB_CCPseudo;
+ case SystemZ::WFSSB_CCPseudo:
+ return SystemZ::WFASB_CCPseudo;
+ default:
+ return std::nullopt;
}
}
@@ -1319,13 +1333,26 @@ void SystemZInstrInfo::genAlternativeCodeSequence(
static void getSplitFMAOpcodes(unsigned FMAOpc, unsigned &AddOpc,
unsigned &MulOpc) {
switch (FMAOpc) {
- case SystemZ::VFMADB: AddOpc = SystemZ::VFADB; MulOpc = SystemZ::VFMDB; break;
- case SystemZ::VFMASB: AddOpc = SystemZ::VFASB; MulOpc = SystemZ::VFMSB; break;
- case SystemZ::WFMAXB: AddOpc = SystemZ::WFAXB; MulOpc = SystemZ::WFMXB; break;
+ case SystemZ::VFMADB:
+ AddOpc = SystemZ::VFADB;
+ MulOpc = SystemZ::VFMDB;
+ break;
+ case SystemZ::VFMASB:
+ AddOpc = SystemZ::VFASB;
+ MulOpc = SystemZ::VFMSB;
+ break;
+ case SystemZ::WFMAXB:
+ AddOpc = SystemZ::WFAXB;
+ MulOpc = SystemZ::WFMXB;
+ break;
case SystemZ::WFMADB_CCPseudo:
- AddOpc = SystemZ::WFADB_CCPseudo; MulOpc = SystemZ::WFMDB_CCPseudo; break;
+ AddOpc = SystemZ::WFADB_CCPseudo;
+ MulOpc = SystemZ::WFMDB_CCPseudo;
+ break;
case SystemZ::WFMASB_CCPseudo:
- AddOpc = SystemZ::WFASB_CCPseudo; MulOpc = SystemZ::WFMSB_CCPseudo; break;
+ AddOpc = SystemZ::WFASB_CCPseudo;
+ MulOpc = SystemZ::WFMSB_CCPseudo;
+ break;
default:
llvm_unreachable("Expected FMA opcode.");
}
@@ -1399,8 +1426,7 @@ void SystemZInstrInfo::reassociateFMA(
getIntersectedFlags(); // XXXXXXXXXx
Register NewVRA = createNewVReg(0);
Register NewVRB = createNewVReg(1);
- unsigned FirstMulIdx =
- Pattern == MachineCombinerPattern::FMA2_P1P0 ? 1 : 0;
+ unsigned FirstMulIdx = Pattern == MachineCombinerPattern::FMA2_P1P0 ? 1 : 0;
unsigned SecondMulIdx = FirstMulIdx == 0 ? 1 : 0;
MachineInstr *MINewA =
BuildMI(*MF, Chain[FirstMulIdx]->getDebugLoc(), get(MulOpc), NewVRA)
@@ -1408,7 +1434,7 @@ void SystemZInstrInfo::reassociateFMA(
.add(Chain[FirstMulIdx]->getOperand(2));
MachineInstr *MINewB =
BuildMI(*MF, Chain[SecondMulIdx]->getDebugLoc(), get(FMAOpc), NewVRB)
- .add(Chain[SecondMulIdx]->getOperand(1))
+ .add(Chain[SecondMulIdx]->getOperand(1))
.add(Chain[SecondMulIdx]->getOperand(2))
.addReg(NewVRA);
MachineInstr *MINewC =
@@ -1525,11 +1551,11 @@ void SystemZInstrInfo::reassociateFMA(
deleteOld();
}
-bool
-SystemZInstrInfo::accumulateInstrSeqToRootLatency(MachineInstr &Root) const {
+bool SystemZInstrInfo::accumulateInstrSeqToRootLatency(
+ MachineInstr &Root) const {
// This doesn't make much sense for FMA patterns as they typically use an
// extra Add to do things in parallell.
- if (IsReassociableFMA(&Root)) // XXXXXXXXXXXX
+ if (IsReassociableFMA(&Root)) // XXXXXXXXXXXX
return false;
return true;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 6394a3ef92..9e64927a15 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -256,8 +256,7 @@ public:
Register FalseReg) const override;
void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
MachineInstr::MIFlag Flag) const;
- MachineInstr *optimizeLoadInstr(MachineInstr &MI,
- MachineRegisterInfo *MRI,
+ MachineInstr *optimizeLoadInstr(MachineInstr &MI, MachineRegisterInfo *MRI,
Register &FoldAsLoadDefReg,
MachineInstr *&DefMI) const override;
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
@@ -313,13 +312,12 @@ public:
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const override;
- void reassociateFMA(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
+ void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override;
- int getExtendResourceLenLimit() const override { return 0; } //XXX
+ int getExtendResourceLenLimit() const override { return 0; } // XXX
// SystemZ specific version of setSpecialOperandAttr that copies Flags to
// MI and clears nuw, nsw, and exact flags.
void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index af2778792c..6bde2efeeb 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -30,9 +30,9 @@
using namespace llvm;
static cl::opt<bool>
-EnableMachineCombinerPass("systemz-machine-combiner",
- cl::desc("Enable the machine combiner pass"),
- cl::init(true), cl::Hidden);
+ EnableMachineCombinerPass("systemz-machine-combiner",
+ cl::desc("Enable the machine combiner pass"),
+ cl::init(true), cl::Hidden);
// NOLINTNEXTLINE(readability-identifier-naming)
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index c8b5152adf..2254236986 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -548,8 +548,7 @@ public:
Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
const MachineRegisterInfo *MRI) const override;
- MachineInstr *optimizeLoadInstr(MachineInstr &MI,
- MachineRegisterInfo *MRI,
+ MachineInstr *optimizeLoadInstr(MachineInstr &MI, MachineRegisterInfo *MRI,
Register &FoldAsLoadDefReg,
MachineInstr *&DefMI) const override;
``````````
</details>
https://github.com/llvm/llvm-project/pull/83546
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