[llvm] [AMDGPU] Move renamedInGFX9 from TableGen to SIInstrInfo helper function/macro to free up a bit slot (PR #82787)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 1 00:07:04 PST 2024
================
@@ -9115,14 +9115,45 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
}
}
+#define GENERATE_RENAMED_GFX9_CASES(OPCODE) \
+ case OPCODE##_dpp: \
+ case OPCODE##_e32: \
+ case OPCODE##_e64: \
+ case OPCODE##_e64_dpp: \
+ case OPCODE##_sdwa:
+
+static bool isRenamedInGFX9(int Opcode) {
+ switch (Opcode) {
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADDC_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADD_CO_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADD_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBBREV_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBB_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBREV_CO_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBREV_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUB_CO_U32)
+ GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUB_U32)
+ //
+ case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
+ case AMDGPU::V_FMA_F16_gfx9_e64:
+ case AMDGPU::V_INTERP_P2_F16:
+ case AMDGPU::V_MAD_F16_e64:
+ case AMDGPU::V_MAD_U16_e64:
+ case AMDGPU::V_MAD_I16_e64:
+ return true;
+ default:
+ return false;
+ }
+}
+
int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode);
unsigned Gen = subtargetEncodingFamily(ST);
- if ((get(Opcode).TSFlags & SIInstrFlags::renamedInGFX9) != 0 &&
- ST.getGeneration() == AMDGPUSubtarget::GFX9)
+ if (isRenamedInGFX9(Opcode) && ST.getGeneration() == AMDGPUSubtarget::GFX9) {
----------------
arsenm wrote:
```suggestion
if (ST.getGeneration() == AMDGPUSubtarget::GFX9 && isRenamedInGFX9(Opcode)) {
```
https://github.com/llvm/llvm-project/pull/82787
More information about the llvm-commits
mailing list