[llvm] [RISCV] Support scheduling VCIX instructions (PR #83427)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

> At the very least all of the VCIX instructions need to go through VCQ and occupy the arithmetic sequencer for VLEN*LMUL/DLEN cycles.

Yeah you are right. And it depends on the implementation of co-processor, so it's really hard to model it staticly in schedule model.

> Should we add a test case?

The test should be reduced, it's too large.

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I just provided a thought/way to fix (temporarily?) the problem, please feel free to create thorough fix as I don't really know the details about x280's microarchitecture.

https://github.com/llvm/llvm-project/pull/83427