[llvm] [RISCV] Support scheduling VCIX instructions (PR #83427)

[Craig Topper via llvm-commits]

topperc wrote:

I think the cycle simulation in the scheduler is keeping the loads in the pending queue instead of the available queue so they aren't in consideration for scheduling. So they aren't available as choices to reduce register pressure.

At the very least all of the VCIX instructions need to go through VCQ and occupy the arithmetic sequencer for VLEN*LMUL/DLEN cycles.

https://github.com/llvm/llvm-project/pull/83427