[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Sergei Barannikov via llvm-commits]

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@@ -88,23 +88,26 @@ unsigned PseudoLoweringEmitter::addDagOperandMapping(
 
       // Normal operands should always have the same type, or we have a
       // problem.
-      // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
-      assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
+
       // FIXME: Are the message operand types backward?
-      if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
+      if (DI->getDef() != Insn.Operands[i].Rec) {
         PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
                             "', operand type '" + DI->getDef()->getName() +
                             "' does not match expansion operand type '" +
-                            Insn.Operands[BaseIdx + i].Rec->getName() + "'");
+                            Insn.Operands[i].Rec->getName() + "'");
         PrintFatalNote(DI->getDef(),
                        "Value was assigned at the following location:");
       }
       // Source operand maps to destination operand. The Data element
       // will be filled in later, just set the Kind for now. Do it
       // for each corresponding MachineInstr operand, not just the first.
-      for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
+      for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) {
         OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
+      }
       OpsAdded += Insn.Operands[i].MINumOperands;
+      if (Insn.Operands[i].MINumOperands > 0)
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s-barannikov wrote:

This can be asserted.

https://github.com/llvm/llvm-project/pull/83436